Processing-in-memory(pim) device

ABSTRACT

A processing-in-memory (PIM) device includes memory banks configured to perform a read operation and a write operation in a normal mode, and to perform a first data providing operation in an accelerator mode, a global buffer configured to perform a second data providing operation in the accelerator mode, processing elements configured to perform at least one of a first arithmetic operation and a second arithmetic operation using at least one of the first data and the second data in the accelerator mode, a command decoder configured to output a normal mode control signal or an accelerator mode start signal, and a processor unit configured to store an operation instruction set transmitted from an external device, to transmit the operation instruction set to the processing elements, and to transmit the accelerator mode control signal to the processing elements.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation-in-part of U.S. patent application Ser. No. 17/090,462, filed on Nov. 5, 2020, which claims the benefit of U.S. Provisional Application No. 62/958,223, filed on Jan. 7, 2020, and claims priority to Korean Application No. 10-2020-0006902, filed on Jan. 17, 2020, in the Korean Intellectual Property Office, which are incorporated herein by reference in their entirety.

BACKGROUND 1. Technical Field

Various embodiments of the present disclosure relate to processing-in-memory (PIM) devices and, more particularly, to PIM devices performing a deterministic arithmetic operation.

2. Related Art

Recently, interest in artificial intelligence (AI) has been increasing not only in the information technology industry but also in the financial and medical industries. Accordingly, in various fields, artificial intelligence, more precisely, the introduction of deep learning, is considered and prototyped. One cause of this widespread interest may be due to the improved performance of processors performing arithmetic operations. To improve the performance of artificial intelligence, it may be necessary to increase the number of layers constituting a neural network of the artificial intelligence to educate the artificial intelligence. This trend has continued in recent years, which has led to an exponential increase in the amount of computations required for hardware actually performing the computations. Moreover, if artificial intelligence employs a general hardware system including a memory and a processor which are separated from each other, the performance of the artificial intelligence may be degraded due to a limitation of the amount of data communication between the memory and the processor. In order to solve this problem, a PIM device in which a processor and memory are integrated in one semiconductor chip has been used as a neural network computing device. Because the PIM device directly performs arithmetic operations in the PIM device, a data processing speed in the neural network may be improved.

SUMMARY

A processing-in-memory (PIM) device according to an embodiment of the present disclosure may include memory banks configured to perform a read operation and a write operation in a normal mode, and to perform a first data providing operation in an accelerator mode, a global buffer configured to perform a second data providing operation in the accelerator mode, processing elements configured to perform at least one of a first arithmetic operation and a second arithmetic operation using at least one of the first data and the second data in the accelerator mode, a command decoder configured to output a normal mode control signal or an accelerator mode start signal, and a processor unit configured to store an operation instruction set transmitted from an external device, to transmit the operation instruction set to the processing elements, and to transmit the accelerator mode control signal to the processing elements.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain features of the disclosed technology are illustrated by various embodiments with reference to the attached drawings.

FIG. 1 is a block diagram illustrating a PIM device according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram illustrating an arrangement of memory banks and multiplication/accumulation (MAC) operators included in a PIM device according to a first embodiment of the present disclosure.

FIG. 3 is a block diagram illustrating a configuration of a PIM device according to the first embodiment of the present disclosure.

FIG. 4 illustrates internal command signals outputted from a command decoder and MAC command signals outputted from a MAC command generator in the PIM device of FIG. 3 .

FIG. 5 illustrates an example of a configuration of a MAC command generator included in the PIM device of FIG. 3 .

FIG. 6 illustrates input signals and output signals of the MAC command generator illustrated in FIG. 5 with a timeline.

FIG. 7 illustrates an example of a configuration of a MAC operator included in the PIM device of FIG. 3 .

FIGS. 8 to 14 are block diagrams illustrating operations of the PIM device illustrated in FIG. 3 .

FIG. 15 is a timing diagram illustrating an operation of the PIM device illustrated in FIG. 3 .

FIG. 16 is a block diagram illustrating another configuration of a PIM device according to the first embodiment of the present disclosure.

FIG. 17 illustrates internal command signals outputted from a command decoder and MAC command signals outputted from a MAC command generator in the PIM device of FIG. 16 .

FIG. 18 illustrates an example of a configuration of a MAC command generator included in the PIM device of FIG. 16 .

FIG. 19 illustrates input signals and output signals of the MAC command generator illustrated in FIG. 18 with a timeline.

FIG. 20 illustrates an example of a configuration of a MAC operator included in the PIM device of FIG. 16 .

FIGS. 21 to 25 are block diagrams illustrating operations of the PIM device illustrated in FIG. 16 .

FIG. 26 is a timing diagram an operation of the PIM device illustrated in FIG. 16 .

FIG. 27 is a schematic diagram illustrating an arrangement of memory banks and multiplication/accumulation (MAC) operators included in a PIM device according to a second embodiment of the present disclosure.

FIG. 28 is a block diagram illustrating a configuration of a PIM device according to the second embodiment of the present disclosure.

FIG. 29 is a block diagram illustrating an operation of the PIM device illustrated in FIG. 28 .

FIG. 30 is a timing diagram illustrating an operation of the PIM device illustrated in FIG. 28 .

FIG. 31 is a block diagram illustrating a PIM device according to another embodiment of the present disclosure.

FIG. 32 is a diagram illustrating an example of a configuration of a first processing element included in the PIM device of FIG. 31 .

FIG. 33 is a diagram illustrating another example of a configuration of the first processing element included in the PIM device of FIG. 31 .

FIG. 34 is a diagram illustrating a MAC arithmetic process in an accelerator mode of the PIM device of FIG. 31 .

FIG. 35 is a timing diagram illustrating a normal mode operation and an accelerator mode operation of the PIM device of FIG. 31.

FIG. 36 is a block diagram illustrating a PIM device according to further another embodiment of the present disclosure.

FIG. 37 is a block diagram illustrating a PIM device according to further another embodiment of the present disclosure.

FIG. 38 is a block diagram illustrating an example of a configuration of a first processing element included in the PIM device of FIG. 37 .

FIG. 39 is a block diagram illustrating a PIM device according to further another embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description of embodiments, it will be understood that the terms “first” and “second” are intended to identify elements, but not used to define a particular number or sequence of elements. In addition, when an element is referred to as being located “on,” “over,” “above,” “under,” or “beneath” another element, it is intended to mean relative positional relationship, but not used to limit certain cases for which the element directly contacts the other element, or at least one intervening element is present between the two elements. Accordingly, the terms such as “on,” “over,” “above,” “under,” “beneath,” “below,” and the like that are used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present disclosure. Further, when an element is referred to as being “connected” or “coupled” to another element, the element may be electrically or mechanically connected or coupled to the other element directly, or may be electrically or mechanically connected or coupled to the other element indirectly with one or more additional elements between the two elements. Moreover, when a parameter is referred to as being “predetermined,” it may be intended to mean that a value of the parameter is determined in advance of when the parameter is used in a process or an algorithm. The value of the parameter may be set when the process or the algorithm starts or may be set during a period in which the process or the algorithm is executed. A logic “high” level and a logic “low” level may be used to describe logic levels of electric signals. A signal having a logic “high” level may be distinguished from a signal having a logic “low” level. For example, when a signal having a first voltage corresponds to a signal having a logic “high” level, a signal having a second voltage may correspond to a signal having a logic “low” level. In an embodiment, the logic “high” level may be set as a voltage level which is higher than a voltage level of the logic “low” level. Meanwhile, logic levels of signals may be set to be different or opposite according to embodiment. For example, a certain signal having a logic “high” level in one embodiment may be set to have a logic “low” level in another embodiment.

Various embodiments of the present disclosure will be described hereinafter in detail with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

Various embodiments are directed to processing-in-memory (PIM) devices which are capable of performing a deterministic arithmetic operation at a high speed.

FIG. 1 is a block diagram illustrating a PIM device according to an embodiment of the present disclosure. As illustrated in FIG. 1 , the PIM device 10 may include a data storage region 11, an arithmetic circuit 12, an interface (I/F) 13-1, and a data (DQ) input/output (I/O) pad 13-2. The data storage region 11 may include a first storage region and a second storage region. In an embodiment, the first storage region and the second storage region may be a first memory bank and a second memory bank, respectively. In another embodiment, the first data storage region and the second storage region may be a memory bank and buffer memory, respectively. The data storage region 11 may include a volatile memory element or a non-volatile memory element. For an embodiment, the data storage region 11 may include both a volatile memory element and a non-volatile memory element.

The arithmetic circuit 12 may perform an arithmetic operation on the data transferred from the data storage region 11. In an embodiment, the arithmetic circuit 12 may include a multiplying-and-accumulating (MAC) operator. The MAC operator may perform a multiplying calculation on the data transferred from the data storage region 11 and perform an accumulating calculation on the multiplication result data. After MAC operations, the MAC operator may output MAC result data. The MAC result data may be stored in the data storage region 11 or output from the PIM device 10 through the data I/O pad 13-2. In an embodiment, the arithmetic circuit 12 may perform additional operations, for example a bias addition operation and an active function operation, for a neural network calculation, for example, an arithmetic operation in a deep learning process. In another embodiment, the PIM device 10 may include a bias addition circuit and active function circuit separated from the arithmetic circuit 12.

The interface 13-1 of the PIM device 10 may receive an external command E_CMD and an input address I_ADDR from an external device. The external device may denote a host or a PIM controller coupled to the PIM device 10. Hereinafter, it may be assumed that the external command E_CMD transmitted to the PIM device 10 is a command requesting the MAC arithmetic operation. That is, the PIM device 10 may perform a MAC arithmetic operation in response to the external command E_CMD. The data I/O pad 13-2 of the PIM device 10 may function as a data communication terminal between a device external to the PIM device 10, for example the PIM controller or a host located outside the PIM system 1. Accordingly, data outputted from the host or the PIM controller may be inputted into the PIM device 10 through the data I/O pad 13-2. Also, data outputted from the PIM device 10 may be inputted to the host or the PIM controller through the data I/O pad 13-2.

In an embodiment, the PIM device 10 may operate in a memory mode or a MAC arithmetic mode. In the event that the PIM device 10 operates in the memory mode, the PIM device 10 may perform a data read operation or a data write operation for the data storage region 11. In the event that the PIM device 10 operates in the MAC arithmetic mode, the arithmetic circuit 12 of the PIM device 10 may receive first data and second data from the data storage region 11 to perform the MAC arithmetic operation. In the event that PIM device 10 operates in the MAC arithmetic mode, the PIM device 10 may also perform the data write operation for the data storage region 11 to execute the MAC arithmetic operation. The MAC arithmetic operation may be a deterministic arithmetic operation performed during a predetermined fixed time. The word “predetermined” as used herein with respect to a parameter, such as a predetermined fixed time or time period, means that a value for the parameter is determined prior to the parameter being used in a process or algorithm. For some embodiments, the value for the parameter is determined before the process or algorithm begins. In other embodiments, the value for the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

FIG. 2 illustrates a disposal structure indicating placement of memory banks BK0, . . . , and BK15 and MAC operators MAC0, . . . , and MAC7 included in a PIM device 100 according to an embodiment of the present disclosure. In an embodiment, the memory banks BK0, . . . , and BK15 and the MAC operators MAC0, . . . , and MAC7 may be included in the data storage region and the arithmetic circuit of the PIM device 10 of FIG. 1 , respectively. Referring to FIG. 2 , the PIM device 100 may include a data storage region and an arithmetic circuit. In an embodiment, the data storage region may include the memory banks BK0, . . . , and BK15. Although the present embodiment illustrates an example in which the data storage region includes the memory banks BK0, . . . , and BK15, the memory banks BK0, . . . , and BK15 are merely examples which are suitable for the data storage region. In some embodiments, the memory banks BK0, . . . , and BK15 may be a memory region corresponding to a volatile memory device, for example, a DRAM device. In an embodiment, each of the memory banks BK0, . . . , and BK15 may be a component unit which is independently activated and may be configured to have the same data bus width as data I/O lines in the PIM device 100. In an embodiment, the memory banks BK0, . . . , and BK15 may operate through interleaving such that an active operation of any one of the memory banks is performed in parallel while another memory bank is selected. Although the present embodiment illustrates an example in which the PIM device 100 includes the memory banks BK0, . . . , and BK15, the number of the memory banks is not limited to 16 and may be different in different embodiments. Each of the memory banks BK0, . . . , and BK15 may include at least one cell array which includes memory unit cells located at cross points of a plurality of rows and a plurality of columns. The memory banks BK0, . . . , and BK15 may include a first group of memory banks (e.g., odd-numbered memory banks BK0, BK2, . . . , and BK14) and a second group of memory banks (e.g., even-numbered memory banks BK1, BK3, . . . , and BK15).

A core circuit may be disposed to be adjacent to the memory banks BK0, . . . , and BK15. The core circuit may include X-decoders XDECs and Y-decoders/IO circuits YDEC/IOs. An X-decoder XDEC may also be referred to as a word line decoder or a row decoder. In an embodiment, two odd-numbered memory banks arrayed to be adjacent to each other in one row among the odd-numbered memory banks BK0, BK2, . . . , and BK14 may share one of the X-decoders XDECs with each other. For example, the first memory bank BK0 and the third memory bank BK2 adjacent to each other in a first row may share one of the X-decoders XDECs, and the fifth memory bank BK4 and the seventh memory bank BK6 adjacent to each other in the first row may also share one of the X-decoders XDECs. Similarly, two even-numbered memory banks arrayed to be adjacent to each other in one row among the even-numbered memory banks BK1, BK3, . . . , and BK15 may share one of the X-decoders XDECs with each other. For example, the second memory bank BK1 and the fourth memory bank BK3 adjacent to each other in a second row may share one of the X-decoders XDECs, and the sixth memory bank BK5 and the eighth memory bank BK7 adjacent to each other in the second row may also share one of the X-decoders XDECs. The X-decoder XDEC may receive a row address from an address latch included in a peripheral circuit PERI and may decode the row address to select and enable one of rows (i.e., word lines) coupled to the memory banks adjacent to the X-decoder XDEC.

The Y-decoders/IO circuits YDEC/IOs may be disposed to be allocated to the memory banks BK0, . . . , and BK15, respectively. For example, the first memory bank BK0 may be allocated to one of the Y-decoders/IO circuits YDEC/IOs, and the second memory bank BK1 may be allocated to another one of the Y-decoders/IO circuits YDEC/IOs. Each of the Y-decoders/IO circuits YDEC/IOs may include a Y-decoder YDEC and an I/O circuit IO. The Y-decoder YDEC may also be referred to as a bit line decoder or a column decoder. The Y-decoder YDEC may receive a column address from an address latch included in the peripheral circuit PERI and may decode the column address to select and enable at least one of columns (i.e., bit lines) coupled to the selected memory bank. Each of the I/O circuits may include an I/O sense amplifier for sensing and amplifying a level of a read datum outputted from the corresponding memory bank during a read operation and a write driver for driving a write datum during a write operation for the corresponding memory bank.

In an embodiment, the arithmetic circuit may include MAC operators MAC0, . . . , and MAC7. Although the present embodiment illustrates an example in which the MAC operators MAC0, . . . , and MAC7 are employed as the arithmetic circuit, the present embodiment may be merely an example of the present disclosure. For example, in some other embodiments, processors other than the MAC operators MAC0, . . . , and MAC7 may be employed as the arithmetic circuit. The MAC operators MAC0, . . . , and MAC7 may be disposed such that one of the odd-numbered memory banks BK0, BK2, . . . , and BK14 and one of the even-numbered memory banks BK1, BK3, . . . , and BK15 share any one of the MAC operators MAC0, . . . , and MAC7 with each other. Specifically, one odd-numbered memory bank and one even-numbered memory bank arrayed in one column to be adjacent to each other may constitute a pair of memory banks sharing one of the MAC operators MAC0, . . . , and MAC7 with each other. One of the MAC operators MAC0, . . . , and MAC7 and a pair of memory banks sharing the one MAC operator with each other will be referred to as ‘a MAC unit’ hereinafter.

In an embodiment, the number of the MAC operators MAC0, . . . , and MAC7 may be equal to the number of the odd-numbered memory banks BK0, BK2, . . . , and BK14 or the number of the even-numbered memory banks BK1, BK3, . . . , and BK15. The first memory bank BK0, the second memory bank BK1, and the first MAC operator MAC0 between the first memory bank BK0 and the second memory bank BK1 may constitute a first MAC unit. In addition, the third memory bank BK2, the fourth memory bank BK3, and the second MAC operator MAC1 between the third memory bank BK2 and the fourth memory bank BK3 may constitute a second MAC unit. The first MAC operator MAC0 included in the first MAC unit may receive first data DA1 outputted from the first memory bank BK0 included in the first MAC unit and second data DA2 outputted from the second memory bank BK1 included in the first MAC unit. In addition, the first MAC operator MAC0 may perform a MAC arithmetic operation of the first data DA1 and the second data DA2. In the event that the PIM device 100 performs a neural network calculation, for example, an arithmetic operation in a deep learning process, one of the first data DA1 and the second data DA2 may be weight data and the other may be vector data. A configuration of any one of the MAC operators MAC0˜MAC7 will be described in more detail hereinafter.

In the PIM device 100, the peripheral circuit PERI may be disposed in a region other than an area in which the memory banks BK0, BK1, . . . , and BK15, the MAC operators MAC0, . . . , and MAC7, and the core circuit are disposed. The peripheral circuit PERI may include a control circuit and a transmission path for a command/address signal, a control circuit and a transmission path for input/output of data, and a power supply circuit. The control circuit for the command/address signal may include a command decoder for decoding a command included in the command/address signal to generate an internal command signal, an address latch for converting an input address into a row address and a column address, a control circuit for controlling various functions of row/column operations, and a control circuit for controlling a delay locked loop (DLL) circuit. The control circuit for the input/output of data in the peripheral circuit PERI may include a control circuit for controlling a read/write operation, a read/write buffer, and an output driver. The power supply circuit in the peripheral circuit PERI may include a reference power voltage generation circuit for generating an internal reference power voltage and an internal power voltage generation circuit for generating an internal power voltage from an external power voltage.

The PIM device 100 according to the present embodiment may operate in any one mode of a memory mode and a MAC arithmetic mode. In the memory mode, the PIM device 100 may operate to perform the same operations as general memory devices. The memory mode may include a memory read operation mode and a memory write operation mode. In the memory read operation mode, the PIM device 100 may perform a read operation for reading out data from the memory banks BK0, BK1, . . . , and BK15 to output the read data, in response to an external request. In the memory write operation mode, the PIM device 100 may perform a write operation for storing data provided by an external device into the memory banks BK0, BK1, . . . , and BK15, in response to an external request.

In the MAC arithmetic mode, the PIM device 100 may perform the MAC arithmetic operation using the MAC operators MAC0, . . . , and MAC7. Specifically, the PIM device 100 may perform the read operation of the first data DA1 for each of the odd-numbered memory banks BK0, BK2, . . . , and BK14 and the read operation of the second data DA2 for each of the even-numbered memory banks BK1, BK3, . . . , and BK15, for the MAC arithmetic operation in the MAC arithmetic mode. In addition, each of the MAC operators MAC0, . . . , and MAC7 may perform the MAC arithmetic operation of the first data DA1 and the second data DA2 which are read out of the memory banks to store a result of the MAC arithmetic operation into the memory bank or to output the result of the MAC arithmetic operation. In some cases, the PIM device 100 may perform a data write operation for storing data to be used for the MAC arithmetic operation into the memory banks before the data read operation for the MAC arithmetic operation is performed in the MAC arithmetic mode.

The operation mode of the PIM device 100 according to the present embodiment may be determined by a command which is transmitted from a host or a controller to the PIM device 100. In an embodiment, if a first external command requesting a read operation or a write operation for the memory banks BK0, BK1, . . . , and BK15 is inputted to the PIM device 100, the PIM device 100 may perform the data read operation or the data write operation in the memory mode. Meanwhile, if a second external command requesting a MAC calculation corresponding to the MAC arithmetic operation is inputted to the PIM device 100, the PIM device 100 may perform the MAC arithmetic operation.

The PIM device 100 may perform a deterministic MAC arithmetic operation. The term “deterministic MAC arithmetic operation” used in the present disclosure may be defined as the MAC arithmetic operation performed in the PIM device 100 during a predetermined fixed time. Thus, the host or the controller may always predict a point in time (or a clock) when the MAC arithmetic operation terminates in the PIM device 100 at a point in time when an external command requesting the MAC arithmetic operation is transmitted from the host or the controller to the PIM device 100. No operation for informing the host or the controller of a status of the MAC arithmetic operation is required while the PIM device 100 performs the deterministic MAC arithmetic operation. In an embodiment, a latency during which the MAC arithmetic operation is performed in the PIM device 100 may be fixed for the deterministic MAC arithmetic operation.

FIG. 3 is a block diagram illustrating a configuration of a PIM device 200 corresponding to the PIM device 100 illustrated in FIG. 3 , and FIG. 4 illustrates an internal command signal I_CMD outputted from a command decoder 250 and a MAC command signal MAC_CMD outputted from a MAC command generator 270 included in the PIM device 200 of FIG. 3 . FIG. 3 illustrates only the first memory bank (BK0) 211, the second memory bank (BK1) 212, and the first MAC operator (MAC0) 220 constituting the first MAC unit among the plurality of MAC units. However, FIG. 3 illustrates merely an example for simplification of the drawing. Accordingly, the following description for the first MAC unit may be equally applicable to the remaining MAC units. Referring to FIG. 3 , the PIM device 200 may include a global I/O line (hereinafter, referred to as a ‘GIO line’) 290. The first memory bank (BK0) 211, the second memory bank (BK1) 212, and the first MAC operator (MAC0) 220 may communicate with each other through the GIO line 290. In an embodiment, the GIO line 290 may be disposed in the peripheral circuit PERI of FIG. 2 .

The PIM device 200 may include a receiving driver (RX) 230, a data I/O circuit (DQ) 240, a command decoder 250, an address latch 260, a MAC command generator 270, and a serializer/deserializer (SER/DES) 280. The command decoder 250, the address latch 260, the MAC command generator 270, and the serializer/deserializer 280 may be disposed in the peripheral circuit PERI of the PIM device 100 illustrated in FIG. 2 . The receiving driver 230 may receive an external command E_CMD and an input address I_ADDR from an external device. The external device may denote a host or a controller coupled to the PIM device 200. Hereinafter, it may be assumed that the external command E_CMD transmitted to the PIM device 200 is a command requesting the MAC arithmetic operation. That is, the PIM device 200 may perform the deterministic MAC arithmetic operation in response to the external command E_CMD. The data I/O circuit 240 may include an I/O pad. The data I/O circuit 240 may be coupled to data I/O line. The PIM device 200 may communicate with the external device through the data I/O circuit 240. The receiving driver 230 may separately output the external command E_CMD and the input address I_ADDR received from the external device. Data DA inputted to the PIM device 200 through the data I/O circuit 240 may be processed by the serializer/deserializer 280 and may be transmitted to the first memory bank (BK0) 211 and the second memory bank (BK1) 212 through the GIO line 290 of the PIM device 200. The data DA outputted from the first memory bank (BK0) 211, the second memory bank (BK1) 212, and the first MAC operator (MAC0) 220 through the GIO line 290 may be processed by the serializer/deserializer 280 and may be outputted to the external device through the data I/O circuit 240. The serializer/deserializer 280 may convert the data DA into parallel data if the data DA are serial data or may convert the data DA into serial data if the data DA are parallel data. For the data conversion, the serializer/deserializer 280 may include a serializer converting parallel data into serial data and a deserializer converting serial data into parallel data.

The command decoder 250 may decode the external command E_CMD outputted from the receiving driver 230 to generate and output the internal command signal I_CMD. As illustrated in FIG. 4 , the internal command signal I_CMD outputted from the command decoder 250 may include first to fourth internal command signals. In an embodiment, the first internal command signal may be a memory active signal ACT_M, the second internal command signal may be a memory read signal READ_M, the third internal command signal may be a MAC arithmetic signal MAC, and the fourth internal command signal may be a result read signal READ_RST. The first to fourth internal command signals outputted from the command decoder 250 may be sequentially inputted to the MAC command generator 270.

In order to perform the deterministic MAC arithmetic operation of the PIM device 200, the memory active signal ACT_M, the memory read signal READ_M, the MAC arithmetic signal MAC, and the result read signal READ_RST outputted from the command decoder 250 may be sequentially generated at predetermined points in time (or clocks). In an embodiment, the memory active signal ACT_M, the memory read signal READ_M, the MAC arithmetic signal MAC, and the result read signal READ_RST may have predetermined latencies, respectively. For example, the memory read signal READ_M may be generated after a first latency elapses from a point in time when the memory active signal ACT_M is generated, the MAC arithmetic signal MAC may be generated after a second latency elapses from a point in time when the memory read signal READ_M is generated, and the result read signal READ_RST may be generated after a third latency elapses from a point in time when the MAC arithmetic signal MAC is generated. No signal is generated by the command decoder 250 until a fourth latency elapses from a point in time when the result read signal READ_RST is generated. The first to fourth latencies may be predetermined and fixed. Thus, the host or the controller outputting the external command E_CMD may predict the points in time when the first to fourth internal command signals constituting the internal command signal I_CMD are generated by the command decoder 250 in advance at a point in time when the external command E_CMD is outputted from the host or the controller.

The address latch 260 may convert the input address I_ADDR outputted from the receiving driver 230 into a bank selection signal BK_S and a row/column address ADDR_R/ADDR_C to output the bank selection signal BK_S and the row/column address ADDR_R/ADDR_C. The bank selection signal BK_S may be inputted to the MAC command generator 270. The row/column address ADDR_R/ADDR_C may be transmitted to the first and second memory banks 211 and 212. One of the first and second memory banks 211 and 212 may be selected by the bank selection signal BK_S. One of rows included in the selected memory bank and one of columns included in the selected memory bank may be selected by the row/column address ADDR_R/ADDR_C. In an embodiment, a point in time when the bank selection signal BK_S is inputted to the MAC command generator 270 may be the same moment as a point in time when the row/column address ADDR_R/ADDR_C is inputted to the first and second memory banks 211 and 212. In an embodiment, the point in time when the bank selection signal BK_S is inputted to the MAC command generator 270 and the point in time when the row/column address ADDR_R/ADDR_C is inputted to the first and second memory banks 211 and 212 may be a point in time when the MAC command is generated to read out data from the first and second memory banks 211 and 212 for the MAC arithmetic operation.

The MAC command generator 270 may output the MAC command signal MAC_CMD in response to the internal command signal I_CMD outputted from the command decoder 250 and the bank selection signal BK_S outputted from the address latch 260. As illustrated in FIG. 4 , the MAC command signal MAC_CMD outputted from the MAC command generator 270 may include first to seventh MAC command signals. In an embodiment, the first MAC command signal may be a MAC active signal RACTV, the second MAC command signal may be a first MAC read signal MAC_RD_BK0, the third MAC command signal may be a second MAC read signal MAC_RD_BK1, the fourth MAC command signal may be a first MAC input latch signal MAC_L1, the fifth MAC command signal may be a second MAC input latch signal MAC_L2, the sixth MAC command signal may be a MAC output latch signal MAC_L3, and the seventh MAC command signal may be a MAC result latch signal MAC_L_RST.

The MAC active signal RACTV may be generated based on the memory active signal ACT_M outputted from the command decoder 250. The first MAC read signal MAC_RD_BK0 may be generated in response to the memory read signal READ_M outputted from the command decoder 250 and the bank selection signal BK_S having a first level (e.g., a logic “low” level) outputted from the address latch 260. The first MAC input latch signal MAC_L1 may be generated at a point in time when a certain time elapses from a point in time when the first MAC read signal MAC_RD_BK0 is generated. For various embodiments, a certain time means a fixed time duration. The second MAC read signal MAC_RD_BK1 may be generated in response to the memory read signal READ_M outputted from the command decoder 250 and the bank selection signal BK_S having a second level (e.g., a logic “high” level) outputted from the address latch 260. The second MAC input latch signal MAC_L2 may be generated at a point in time when a certain time elapses from a point in time when the second MAC read signal MAC_RD_BK1 is generated. The MAC output latch signal MAC_L3 may be generated in response to the MAC arithmetic signal MAC outputted from the command decoder 250. Finally, the MAC result latch signal MAC_L_RST may be generated in response to the result read signal READ_RST outputted from the command decoder 250.

The MAC active signal RACTV outputted from the MAC command generator 270 may control an activation operation for the first and second memory banks 211 and 212. The first MAC read signal MAC_RD_BK0 outputted from the MAC command generator 270 may control a data read operation for the first memory bank 211. The second MAC read signal MAC_RD_BK1 outputted from the MAC command generator 270 may control a data read operation for the second memory bank 212. The first MAC input latch signal MAC_L1 and the second MAC input latch signal MAC_L2 outputted from the MAC command generator 270 may control an input data latch operation of the first MAC operator (MAC0) 220. The MAC output latch signal MAC_L3 outputted from the MAC command generator 270 may control an output data latch operation of the first MAC operator (MAC0) 220. The MAC result latch signal MAC_L_RST outputted from the MAC command generator 270 may control a reset operation of the first MAC operator (MAC0) 220.

As described above, in order to perform the deterministic MAC arithmetic operation of the PIM device 200, the memory active signal ACT_M, the memory read signal READ_M, the MAC arithmetic signal MAC, and the result read signal READ_RST outputted from the command decoder 250 may be sequentially generated at predetermined points in time (or clocks), respectively. Thus, the MAC active signal RACTV, the first MAC read signal MAC_RD_BK0, the second MAC read signal MAC_RD_BK1, the first MAC input latch signal MAC_L1, the second MAC input latch signal MAC_L2, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may also be generated and outputted from the MAC command generator 270 at predetermined points in time after the external command E_CMD is inputted to the PIM device 200, respectively. That is, a time period from a point in time when the first and second memory banks 211 and 212 are activated by the MAC active signal RACTV until a point in time when the first MAC operator (MAC0) 220 is reset by the MAC result latch signal MAC_L_RST may be predetermined, and thus the PIM device 200 may perform the deterministic MAC arithmetic operation.

FIG. 5 illustrates an example of a configuration of the MAC command generator 270 included in the PIM device 200 illustrated in FIG. 3 . Referring to FIG. 5 , the MAC command generator 270 may sequentially receive the memory active signal ACT_M, the memory read signal READ_M, the MAC arithmetic signal MAC, and the result read signal READ_RST from the command decoder 250. In addition, the MAC command generator 270 may also receive the bank selection signal BK_S from the address latch 260. The MAC command generator 270 may output the MAC active signal RACTV, the first MAC read signal MAC_RD_BK0, the second MAC read signal MAC_RD_BK1, the first MAC input latch signal MAC_L1, the second MAC input latch signal MAC_L2, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST in series with certain time intervals. For an embodiment, a certain time interval is a time interval having a fixed duration.

In an embodiment, the MAC command generator 270 may be configured to include an active signal generator 271, a delay circuit 272, an inverter 273, and first to fourth AND gates 274, 275, 276, and 277. The active signal generator 271 may receive the memory active signal ACT_M to generate and output the MAC active signal RACTV. The MAC active signal RACTV outputted from the active signal generator 271 may be transmitted to the first and second memory banks 211 and 212 to activate the first and second memory banks 211 and 212. The delay circuit 272 may receive the memory read signal READ_M and may delay the memory read signal READ_M by a delay time DELAY_T to output the delayed signal of the memory read signal READ_M. The inverter 273 may receive the bank selection signal BK_S and may invert a logic level of the bank selection signal BK_S to output the inverted signal of the bank selection signal BK_S.

The first AND gate 274 may receive the memory read signal READ_M and an output signal of the inverter 273 and may perform a logical AND operation of the memory read signal READ_M and an output signal of the inverter 273 to generate and output the first MAC read signal MAC_RD_BK0. The second AND gate 275 may receive the memory read signal READ_M and the bank selection signal BK_S and may perform a logical AND operation of the memory read signal READ_M and the bank selection signal BK_S to generate and output the second MAC read signal MAC_RD_BK1. The third AND gate 276 may receive an output signal of the delay circuit 272 and an output signal of the inverter 273 and may perform a logical AND operation of the output signals of the delay circuit 272 and the inverter 273 to generate and output the first MAC input latch signal MAC_L1. The fourth AND gate 277 may receive an output signal of the delay circuit 272 and the bank selection signal BK_S and may perform a logical AND operation of the output signal of the delay circuit 272 and the bank selection signal BK_S to generate and output the second MAC input latch signal MAC_L2.

It may be assumed that the memory read signal READ_M inputted to the MAC command generator 270 has a logic “high” level and the bank selection signal BK_S inputted to the MAC command generator 270 has a logic “low” level. A level of the bank selection signal BK_S may change from a logic “low” level into a logic “high” level after a certain time elapses. When the memory read signal READ_M has a logic “high” level and the bank selection signal BK_S has a logic “low” level, the first AND gate 274 may output the first MAC read signal MAC_RD_BK0 having a logic “high” level and the second AND gate 275 may output the second MAC read signal MAC_RD_BK1 having a logic “low” level. The first memory bank 211 may transmit the first data DA1 to the first MAC operator 220 according to a control operation based on the first MAC read signal MAC_RD_BK0 having a logic “high” level. If a level transition of the bank selection signal BK_S occurs so that both of the memory read signal READ_M and the bank selection signal BK_S have a logic “high” level, the first AND gate 274 may output the first MAC read signal MAC_RD_BK0 having a logic “low” level and the second AND gate 275 may output the second MAC read signal MAC_RD_BK1 having a logic “high” level. The second memory bank 212 may transmit the second data DA2 to the first MAC operator 220 according to a control operation based on the second MAC read signal MAC_RD_BK1 having a logic “high” level.

Due to the delay time of the delay circuit 272, the output signals of the third and fourth AND gates 276 and 277 may be generated after the first and second MAC read signals MAC_RD_BK0 and MAC_RD_BK1 are generated. Thus, after the second MAC read signal MAC_RD_BK1 is generated, the third AND gate 276 may output the first MAC input latch signal MAC_L1 having a logic “high” level. The first MAC operator 220 may latch the first data DA1 in response to the first MAC input latch signal MAC_L1 having a logic “high” level. After a certain time elapses from a point in time when the first data DA1 are latched by the first MAC operator 220, the fourth AND gate 277 may output the second MAC input latch signal MAC_L2 having a logic “high” level. The first MAC operator 220 may latch the second data DA2 in response to the second MAC input latch signal MAC_L2 having a logic “high” level. The first MAC operator 220 may start to perform the MAC arithmetic operation after the first and second data DA1 and DA2 are latched.

The MAC command generator 270 may generate the MAC output latch signal MAC_L3 in response to the MAC arithmetic signal MAC outputted from the command decoder 250. The MAC output latch signal MAC_L3 may have the same logic level as the MAC arithmetic signal MAC. For example, if the MAC arithmetic signal MAC having a logic “high” level is inputted to the MAC command generator 270, the MAC command generator 270 may generate the MAC output latch signal MAC_L3 having a logic “high” level. The MAC command generator 270 may generate the MAC result latch signal MAC_L_RST in response to the result read signal READ_RST outputted from the command decoder 250. The MAC result latch signal MAC_L_RST may have the same logic level as the result read signal READ_RST. For example, if the result read signal READ_RST having a logic “high” level is inputted to the MAC command generator 270, the MAC command generator 270 may generate the MAC result latch signal MAC_L_RST having a logic “high” level.

FIG. 6 illustrates input signals and output signals of the MAC command generator 270 illustrated in FIG. 5 along a timeline. In FIG. 6 , signals transmitted from the command decoder 250 to the MAC command generator 270 are illustrated in an upper dotted line box, and signals outputted from the MAC command generator 270 are illustrated in a lower dotted line box. Referring to FIGS. 5 and 6 at a first point in time “T1” of the timeline, the memory active signal ACT_M may be inputted to the MAC command generator 270 and the MAC command generator 270 may output the MAC active signal RACTV. At a second point in time “T2” when a certain time, for example, a first latency L1 elapses from the first point in time “T1”, the memory read signal READ_M having a logic “high” level and the bank selection signal BK_S having a logic “low” level may be inputted to the MAC command generator 270. In response to the memory read signal READ_M having a logic “high” level and the bank selection signal BK_S having a logic “low” level, the MAC command generator 270 may output the first MAC read signal MAC_RD_BK0 having a logic “high” level and the second MAC read signal MAC_RD_BK1 having a logic “low” level in response to the memory read signal READ_M having a logic “high” level and the bank selection signal BK_S having a logic “low” level, as described with reference to FIG. 5 . At a third point in time “T3” when a certain time elapses from the second point in time “T2”, a logic level of the bank selection signal BK_S may change from a logic “low” level into a logic “high” level. In such a case, the MAC command generator 270 may output the first MAC read signal MAC_RD_BK0 having a logic “low” level and the second MAC read signal MAC_RD_BK1 having a logic “high” level, as described with reference to FIG. 5 .

At a fourth point in time “T4” when the delay time DELAY_T elapses from the second point in time “T2”, the MAC command generator 270 may output the first MAC input latch signal MAC_L1 having a logic “high” level and the second MAC input latch signal MAC_L2 having a logic “low” level. The delay time DELAY_T may be set by the delay circuit 272. The delay time DELAY_T may bet to be different according a logic design scheme of the delay circuit 272 and may be fixed once the logic design scheme of the delay circuit 272 is determined. In an embodiment, the delay time DELAY_T may be set to be equal to or greater than a second latency L2. At a fifth point in time “T5” when a certain time elapses from the fourth point in time “T4”, the MAC command generator 270 may output the first MAC input latch signal MAC_L1 having a logic “low” level and the second MAC input latch signal MAC_L2 having a logic “high” level. The fifth point in time “T5” may be a moment when the delay time DELAY_T elapses from the third point in time “T3”.

At a sixth point in time “T6” when a certain time, for example, a third latency L3 elapses from the fourth point in time “T4”, the MAC arithmetic signal MAC having a logic “high” level may be inputted to the MAC command generator 270. In response to the MAC arithmetic signal MAC having a logic “high” level, the MAC command generator 270 may output the MAC output latch signal MAC_L3 having a logic “high” level, as described with reference to FIG. 5 . Subsequently, at a seventh point in time “T7” when a certain time, for example, a fourth latency L4 elapses from the sixth point in time “T6”, the result read signal READ_RST having a logic “high” level may be inputted to the MAC command generator 270. In response to the result read signal READ_RST having a logic “high” level, the MAC command generator 270 may output the MAC result latch signal MAC_L_RST having a logic “high” level, as described with reference to FIG. 5 .

In order to perform the deterministic MAC arithmetic operation, moments when the internal command signals ACT_M, READ_M, MAC, and READ_RST generated by the command decoder 250 are inputted to the MAC command generator 270 may be fixed and moments when the MAC command signals RACTV, MAC_RD_BK0, MAC_RD_BK1, MAC_L1, MAC_L2, MAC_L3, and MAC_L_RST are outputted from the MAC command generator 270 in response to the internal command signals ACT_M, READ_M, MAC, and READ_RST may also be fixed. Thus, all of the first latency L1 between the first point in time “T1” and the second point in time “T2”, the second latency L2 between the second point in time “T2” and the fourth point in time “T4”, the third latency L3 between the fourth point in time “T4” and the sixth point in time “T6”, and the fourth latency L4 between the sixth point in time “T6” and the seventh point in time “T7” may have fixed values.

In an embodiment, the first latency L1 may be defined as a time it takes to activate both of the first and second memory banks based on the MAC active signal RACTV. The second latency L2 may be defined as a time it takes to read the first and second data out of the first and second memory banks BK0 and BK1 based on the first and second MAC read signals MAC_RD_BK0 and MAC_RD_BK1 and to input the first and second data DA1 and DA2 into the first MAC operator (MAC0) 220. The third latency L3 may be defined as a time it takes to latch the first and second data DA1 and DA2 in the first MAC operator (MAC0) 220 based on the first and second MAC input latch signals MAC_L1 and MAC_L2 and it takes the first MAC operator (MAC0) 220 to perform the MAC arithmetic operation of the first and second data. The fourth latency L4 may be defined as a time it takes to latch the output data in the first MAC operator (MAC0) 220 based on the MAC output latch signal MAC_L3.

FIG. 7 illustrates an example of a configuration of the first MAC operator (MAC0) 220 included in the PIM device 200 illustrated in FIG. 3 . Referring to FIG. 7 , the first MAC operator (MAC0) 220 may be configured to include a data input circuit 221, a MAC circuit 222, and a data output circuit 223. The data input circuit 221 may be configured to include a first input latch 221-1 and a second input latch 221-2. The MAC circuit 222 may be configured to include a multiplication logic circuit 222-1 and an addition logic circuit 222-2. The data output circuit 223 may be configured to include an output latch 223-1, a transfer gate 223-2, a delay circuit 223-3, and an inverter 223-4. In an embodiment, the first input latch 221-1, the second input latch 221-2, and the output latch 223-1 may be realized using flip-flops.

The data input circuit 221 of the first MAC operator (MAC0) 220 may be synchronized with the first and second MAC input latch signals MAC_L1 and MAC_L2 to receive and output the first and second data DA1 and DA2 inputted through the GIO line 290 to the MAC circuit 222. Specifically, the first data DA1 may be transmitted from the first memory bank BK0 (211 of FIG. 3 ) to the first input latch 221-1 of the data input circuit 221 through the GIO line 290, in response to the first MAC read signal MAC_RD_BK0 having a logic “high” level outputted from the MAC command generator (270 of FIG. 3 ). The second data DA2 may be transmitted from the second memory bank BK1 (212 of FIG. 2 ) to the second input latch 221-2 of the data input circuit 221 through the GIO line 290, in response to the second MAC read signal MAC_RD_BK1 having a logic “high” level outputted from the MAC command generator 270. The first input latch 221-1 may output the first data DA1 to the MAC circuit 222 in synchronization with the first MAC input latch signal MAC_L1 having a logic “high” level outputted from the MAC command generator 270 (270 of FIG. 3 ). The second input latch 221-2 may output the second data DA2 to the MAC circuit 222 in synchronization with the second MAC input latch signal MAC_L2 having a logic “high” level outputted from the MAC command generator (270 of FIG. 3 ). As described with reference to FIG. 5 , the second MAC input latch signal MAC_L2 may be generated at a moment (corresponding to the fifth point in time “T5” of FIG. 6 ) when a certain time elapses from a moment (corresponding to the fourth point in time “T4” of FIG. 6 ) when the first MAC input latch signal MAC_L1 is generated. Thus, after the first data DA1 is inputted to the MAC circuit 222, the second data DA2 may then be inputted to the MAC circuit 222.

The MAC circuit 222 may perform a multiplying calculation and an accumulative adding calculation for the first and second data DA1 and DA2. The multiplication logic circuit 222-1 of the MAC circuit 222 may include a plurality of multipliers 222-11. Each of the plurality of multipliers 222-11 may perform a multiplying calculation of the first data DA1 outputted from the first input latch 221-1 and the second data DA2 outputted from the second input latch 221-2 and may output the result of the multiplying calculation. Bit values constituting the first data DA1 may be separately inputted to the multipliers 222-11. Similarly, bit values constituting the second data DA2 may also be separately inputted to the multipliers 222-11. For example, if each of the first and second data DA1 and DA2 is comprised of an ‘N’-bit binary stream and the number of the multipliers 222-11 is ‘M’, the first data DA1 having ‘N/M’ bits and the second data DA2 having ‘N/M’ bits may be inputted to each of the multipliers 222-11. That is, each of the multipliers 222-11 may be configured to perform a multiplying calculation of first ‘N/M’-bit data and second ‘N/M’-bit data. Multiplication result data outputted from each of the multipliers 222-11 may have ‘2N/M’ bits.

The addition logic circuit 222-2 of the MAC circuit 222 may include a plurality of adders 222-21. Although not shown in the drawings, the plurality of adders 222-21 may be disposed to provide a tree structure including a plurality of stages. Each of the adders 222-21 disposed at a first stage may receive two sets of multiplication result data from two of the multipliers 222-11 included in the multiplication logic circuit 222-1 and may perform an adding calculation of the two sets of multiplication result data to output addition result data. Each of the adders 222-21 disposed at a second stage may receive two sets of addition result data from two of the adders 222-21 disposed at the first stage and may perform an adding calculation of the two sets of addition result data to output addition result data. The adders 222-21 disposed at a last stage may receive two sets of addition result data from two adders 222-21 disposed at the previous stage and may perform an adding calculation of the two sets of addition result data to output the addition result data. The adders 222-21 constituting the addition logic circuit 222-2 may include an adder for performing an accumulative adding calculation of the addition result data outputted from the adder 222-21 disposed at the last stage and previous MAC result data stored in the output latch 223-1 of the data output circuit 223.

The data output circuit 223 may output MAC result data DA_MAC outputted from the MAC circuit 222 to the GIO line 290. Specifically, the output latch 223-1 of the data output circuit 223 may latch the MAC result data DA_MAC outputted from the MAC circuit 222 and may output the latched data of the MAC result data DA_MAC in synchronization with the MAC output latch signal MAC_L3 having a logic “high” level outputted from the MAC command generator (270 of FIG. 3 ). The MAC result data DA_MAC outputted from the output latch 223-1 may be fed back to the MAC circuit 222 for the accumulative adding calculation. In addition, the MAC result data DA_MAC may be inputted to the transfer gate 223-2, and the transfer gate 223-2 may output the MAC result data DA_MAC to the GIO line 290. The output latch 223-1 may be initialized if a latch reset signal LATCH_RST is inputted to the output latch 223-1. In such a case, all of data latched by the output latch 223-1 may be removed. In an embodiment, the latch reset signal LATCH_RST may be activated by generation of the MAC result latch signal MAC_L_RST having a logic “high” level and may be inputted to the output latch 223-1.

The MAC result latch signal MAC_L_RST outputted from the MAC command generator 270 may be inputted to the transfer gate 223-2, the delay circuit 223-3, and the inverter 223-4. The inverter 223-4 may inversely buffer the MAC result latch signal MAC_L_RST to output the inversely buffered signal of the MAC result latch signal MAC_L_RST to the transfer gate 223-2. The transfer gate 223-2 may transfer the MAC result data DA_MAC from the output latch 223-1 to the GIO line 290 in response to the MAC result latch signal MAC_L_RST having a logic “high” level. The delay circuit 223-3 may delay the MAC result latch signal MAC_L_RST by a certain time to generate and output a latch control signal PINSTB.

FIGS. 8 to 14 are block diagrams illustrating operations of the PIM device 200 illustrated in FIG. 3 . In FIGS. 8 to 14 , the same reference numerals or the same reference symbols as used in FIG. 3 denote the same elements. First, referring to FIG. 8 , if the external command E_CMD requesting the MAC arithmetic operation and the input address I_ADDR are transmitted from an external device to the receiving driver 230, the receiving driver 230 may output the external command E_CMD and the input address I_ADDR to the command decoder 250 and the address latch 260, respectively. The command decoder 250 may decode the external command E_CMD to generate and transmit the memory active signal ACT_M to the MAC command generator 270. The address latch 260 receiving the input address I_ADDR may generate and transmit the bank selection signal BK_S to the MAC command generator 270. The MAC command generator 270 may generate and output the MAC active signal RACTV in response to the memory active signal ACT_M and the bank selection signal BK_S. The MAC active signal RACTV may be transmitted to the first memory bank (BK0) 211 and the second memory bank (BK1) 212. The first memory bank (BK0) 211 and the second memory bank (BK1) 212 may be activated by the MAC active signal RACTV.

Next, referring to FIG. 9 , the command decoder 250 may generate and output the memory read signal READ_M having a logic “high(H)” level to the MAC command generator 270. In addition, the address latch 260 may generate and output the bank selection signal BK_S having a logic “low(L)” level to the MAC command generator 270. In response to the memory read signal READ_M having a logic “high(H)” level and the bank selection signal BK_S having a logic “low(L)” level, the MAC command generator 270 may generate and output the first MAC read signal MAC_RD_BK0 having a logic “high(H)” level and the second MAC read signal MAC_RD_BK1 having a logic “low(L)” level, as described with reference to FIG. 4 . The first MAC read signal MAC_RD_BK0 having a logic “high(H)” level, together with the row/column address ADDR_R/ADDR_C, may be transmitted to the first memory bank (BK0) 211. The second MAC read signal MAC_RD_BK1 having a logic “low(L)” level, together with the row/column address ADDR_R/ADDR_C, may be transmitted to the second memory bank (BK1) 212. The first data DA1 may be read out of the first memory bank (BK0) 211 by the first MAC read signal MAC_RD_BK0 having a logic “high(H)” level and may be transmitted to the first MAC operator (MAC0) 220 through the GIO line 290.

Next, referring to FIG. 10 , a logic level of the bank selection signal BK_S may change from a logic “low(L)” level into a logic “high(H)” level while the memory read signal READ_M maintains a logic “high(H)” level. In such a case, as described with reference to FIG. 5 , the MAC command generator 270 may generate and output the first MAC read signal MAC_RD_BK0 having a logic “low(L)” level and the second MAC read signal MAC_RD_BK1 having a logic “high(H)” level. The first MAC read signal MAC_RD_BK0 having a logic “low(L)” level, together with the row/column address ADDR_R/ADDR_C, may be transmitted to the first memory bank (BK0) 211. The second MAC read signal MAC_RD_BK1 having a logic “high(H)” level, together with the row/column address ADDR_R/ADDR_C, may be transmitted to the second memory bank (BK1) 212. The second data DA2 may be read out of the second memory bank (BK1) 212 by the second MAC read signal MAC_RD_BK1 having a logic “high(H)” level and may be transmitted to the first MAC operator (MAC0) 220 through the GIO line 290.

Next, referring to FIG. 11 , a logic level of the memory read signal READ_M transmitted from the command decoder 250 to the MAC command generator 270 may change from a logic “high(H)” level into a logic “low(L)” level. In addition, a logic level of the bank selection signal BK_S transmitted from the address latch 260 to the MAC command generator 270 may change from a logic “high(H)” level into a logic “low(L)” level. In such a case, the MAC command generator 270 may generate and output the first MAC input latch signal MAC_L1 having a logic “high(H)” level and the second MAC input latch signal MAC_L2 having a logic “low(L)” level. A point in time when the first MAC input latch signal MAC_L1 having a logic “high(H)” level and the second MAC input latch signal MAC_L2 having a logic “low(L)” level are outputted from the MAC command generator 270 may be determined by a delay time of the delay circuit (271 of FIG. 4 ), as described with reference to FIG. 5 . The first MAC input latch signal MAC_L1 having a logic “high(H)” level and the second MAC input latch signal MAC_L2 having a logic “low(L)” level outputted from the MAC command generator 270 may be transmitted to the first MAC operator (MAC0) 220. As described with reference to FIG. 7 , the first MAC operator (MAC0) 220 may perform a latch operation of the first data DA1.

Next, referring to FIG. 12 , a logic level of the bank selection signal BK_S transmitted from the address latch 260 to the MAC command generator 270 may change from a logic “low(L)” level into a logic “high(H)” level while the memory read signal READ_M maintains a logic “low(L)” level. In such a case, the MAC command generator 270 may generate and output the first MAC input latch signal MAC_L1 having a logic “low(L)” level and the second MAC input latch signal MAC_L2 having a logic “high(H)” level. A point in time when the first MAC input latch signal MAC_L1 having a logic “low(L)” level and the second MAC input latch signal MAC_L2 having a logic “high(H)” level are outputted from the MAC command generator 270 may be determined by a delay time of the delay circuit (271 of FIG. 5 ), as described with reference to FIG. 5 . The first MAC input latch signal MAC_L1 having a logic “low(L)” level and the second MAC input latch signal MAC_L2 having a logic “high(H)” level outputted from the MAC command generator 270 may be transmitted to the first MAC operator (MAC0) 220. As described with reference to FIG. 7 , the first MAC operator (MAC0) 220 may perform a latch operation of the second data DA2. After the latch operations of the first and second data DA1 and DA2 terminate, the first MAC operator (MAC0) 220 may perform the MAC arithmetic operation and may generate the MAC result data DA_MAC. The MAC result data DA_MAC generated by the first MAC operator (MAC0) 220 may be inputted to the output latch 223-1 included in the first MAC operator (MAC0) 220.

Next, referring to FIG. 13 , the command decoder 250 may output and transmit the MAC arithmetic signal MAC having a logic “high(H)” level to the MAC command generator 270. The MAC command generator 270 may generate and output the MAC output latch signal MAC_L3 having a logic “high” level in response to the MAC arithmetic signal MAC having a logic “high(H)” level. The MAC output latch signal MAC_L3 having a logic “high” level may be transmitted to the first MAC operator (MAC0) 220. As described with reference to FIG. 7 , the output latch (223-1 of FIG. 7 ) of the first MAC operator (MAC0) 220 may be synchronized with the MAC output latch signal MAC_L3 having a logic “high” level to transfer the MAC result data DA_MAC outputted from the MAC circuit 222 of the first MAC operator (MAC0) 220 to the transfer gate (233-2 of FIG. 7 ) of the first MAC operator (MAC0) 220. The MAC result data DA_MAC outputted from the output latch (223-1 of FIG. 7 ) may be fed back to the addition logic circuit (222-2 of FIG. 7 ) for the accumulative adding calculation.

Next, referring to FIG. 14 , the command decoder 250 may output and transmit the result read signal READ_RST having a logic “high(H)” level to the MAC command generator 270. The MAC command generator 270 may generate and output the MAC result latch signal MAC_L_RST having a logic “high” level in response to the result read signal READ_RST having a logic “high(H)” level. The MAC result latch signal MAC_L_RST having a logic “high” level may be transmitted to the first MAC operator (MAC0) 220. As described with reference to FIG. 7 , the first MAC operator (MAC0) 220 may output the MAC result data DA_MAC to the GIO line 290 in response to the MAC result latch signal MAC_L_RST having a logic “high” level and may also reset the output latch (223-1 of FIG. 6 ) included in the first MAC operator (MAC0) 220 in response to the MAC result latch signal MAC_L_RST having a logic “high” level. The MAC result data DA_MAC transmitted to the GIO line 290 may be outputted to an external device through the serializer/deserializer 280 and the data I/O circuit 240.

FIG. 15 is a timing diagram illustrating an operation of the PIM device 200 illustrate in FIG. 3 . Referring to FIG. 15 , at a first point in time “T1”, the MAC command generator 270 may be synchronized with a falling edge of a clock signal CLK to generate and output the first MAC read signal MAC_RD_BK0 (R1) having a logic “high(H)” level. The first memory bank (BK0) 211 may be selected by the first MAC read signal MAC_RD_BK0 (R1) having a logic “high(H)” level so that the first data DA1 are read out of the first memory bank (BK0) 211. At a second point in time “T2”, the MAC command generator 270 may be synchronized with a falling edge of the clock signal CLK to generate and output the second MAC read signal MAC_RD_BK1 (R2) having a logic “high(H)” level. The second memory bank (BK1) 212 may be selected by the second MAC read signal MAC_RD_BK1 (R2) having a logic “high(H)” level so that the second data DA2 are read out of the second memory bank (BK1) 212. At a third point in time “T3”, the MAC command generator 270 may be synchronized with a falling edge of the clock signal CLK to generate and output the MAC arithmetic signal MAC having a logic “high(H)” level. The first MAC operator (MAC0) 220 may perform the multiplying calculations and the adding calculations of the first and second data DA1 and DA2 to generate the MAC result data DA_MAC, in response to the MAC arithmetic signal MAC having a logic “high(H)” level. At a fourth point in time “T4”, the MAC command generator 270 may be synchronized with a falling edge of the clock signal CLK to generate and output the MAC result latch signal MAC_L_RST (RST) having a logic “high” level. The MAC result data DA_MAC generated by the first MAC operator (MAC0) 220 may be transmitted to the GIO line 290 by the MAC result latch signal MAC_L_RST (RST) having a logic “high” level.

FIG. 16 is a block diagram illustrating another configuration of a PIM device 300 according to an embodiment of the present disclosure, and FIG. 17 illustrates an internal command signal I_CMD outputted from a command decoder 350 of the PIM device 300 and a MAC command signal MAC_CMD outputted from a MAC command generator 370 of the PIM device 300. FIG. 16 illustrates only a first memory bank (BK0) 311, a second memory bank (BK1) 312, and a first MAC operator (MAC0) 320 constituting a first MAC unit among the plurality of MAC units. However, FIG. 16 illustrates merely an example for simplification of the drawing. Accordingly, the following description for the first MAC unit may be equally applicable to the remaining MAC units.

Referring to FIG. 16 , the PIM device 300 may be configured to include the first memory bank (BK0) 311, the second memory bank (BK1) 312, and the first MAC operator (MAC0) 320. The PIM device 300 according to the present embodiment may include a GIO line 390, a first bank input/output (BIO) line 391, and a second BIO line 392 acting as data transmission lines. Data communication of the first memory bank (BK0) 311, the second memory bank (BK1) 312, and the first MAC operator (MAC0) 320 may be achieved through the GIO line 390. Only the data transmission between the first memory bank (BK0) 311 and the first MAC operator (MAC0) 320 may be achieved through the first BIO line 391, and only the data transmission between the second memory bank (BK1) 312 and the first MAC operator (MAC0) 320 may be achieved through the second BIO line 392. Thus, the first MAC operator (MAC0) 320 may directly receive first data and second data from the first and second memory banks (BK0 and BK1) 311 and 312 through the first BIO line 391 and the second BIO line 392 without using the GIO line 390.

The PIM device 300 may further include a receiving driver (RX) 330, a data I/O circuit (DQ) 340, the command decoder 350, an address latch 360, the MAC command generator 370, and a serializer/deserializer (SER/DES) 380. The command decoder 350, the address latch 360, the MAC command generator 370, and the serializer/deserializer 380 may be disposed in the peripheral circuit PERI of the PIM device 100 illustrated in FIG. 2 . The receiving driver 330 may receive an external command E_CMD and an input address I_ADDR from an external device. The external device may denote a host or a controller coupled to the PIM device 300. Hereinafter, it may be assumed that the external command E_CMD transmitted to the PIM device 300 is a command requesting the MAC arithmetic operation. That is, the PIM device 300 may perform the deterministic MAC arithmetic operation in response to the external command E_CMD. The data I/O circuit 340 may include a data I/O pad. The data I/O pad may be coupled with an data I/O line. The PIM device 300 communicates with the external device through the data I/O circuit 340.

The receiving driver 330 may separately output the external command E_CMD and the input address I_ADDR received from the external device. Data DA inputted to the PIM device 300 through the data I/O circuit 340 may be processed by the serializer/deserializer 380 and may be transmitted to the first memory bank (BK0) 311 and the second memory bank (BK1) 312 through the GIO line 390 of the PIM device 300. The data DA outputted from the first memory bank (BK0) 311, the second memory bank (BK1) 312, and the first MAC operator (MAC0) 320 through the GIO line 390 may be processed by the serializer/deserializer 380 and may be outputted to the external device through the data I/O circuit 340. The serializer/deserializer 380 may convert the data DA into parallel data if the data DA are serial data or may convert the data DA into serial data if the data DA are parallel data. For the data conversion, the serializer/deserializer 380 may include a serializer for converting parallel data into serial data and a deserializer for converting serial data into parallel data.

The command decoder 350 may decode the external command E_CMD outputted from the receiving driver 330 to generate and output the internal command signal I_CMD. As illustrated in FIG. 17 , the internal command signal I_CMD outputted from the command decoder 350 may include first to third internal command signals. In an embodiment, the first internal command signal may be a memory active signal ACT_M, the second internal command signal may be a MAC arithmetic signal MAC, and the third internal command signal may be a result read signal READ_RST. The first to third internal command signals outputted from the command decoder 350 may be sequentially inputted to the MAC command generator 370.

In order to perform the deterministic MAC arithmetic operation of the PIM device 300, the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST outputted from the command decoder 350 may be sequentially generated at predetermined points in time (or clocks). In an embodiment, the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST may have predetermined latencies, respectively. For example, the MAC arithmetic signal MAC may be generated after a first latency elapses from a point in time when the memory active signal ACT_M is generated, and the result read signal READ_RST may be generated after a third latency elapses from a point in time when the MAC arithmetic signal MAC is generated. No signal is generated by the command decoder 350 until a fourth latency elapses from a point in time when the result read signal READ_RST is generated. The first to fourth latencies may be predetermined and fixed. Thus, the host or the controller outputting the external command E_CMD may predict the points in time when the first to third internal command signals constituting the internal command signal I_CMD are generated by the command decoder 350 in advance at a point in time when the external command E_CMD is outputted from the host or the controller. That is, the host or the controller may predict a point in time (or a clock) when the MAC arithmetic operation terminates in the PIM device 300 after the external command E_CMD requesting the MAC arithmetic operation is transmitted from the host or the controller to the PIM device 300, even without receiving any signals from the PIM device 300.

The address latch 360 may convert the input address I_ADDR outputted from the receiving driver 330 into a row/column address ADDR_R/ADDR_C to output the row/column address ADDR_R/ADDR_C. The row/column address ADDR_R/ADDR_C outputted from the address latch 360 may be transmitted to the first and second memory banks 311 and 312. According to the present embodiment, the first data and the second data to be used for the MAC arithmetic operation may be simultaneously read out of the first and second memory banks (BK0 and BK1) 311 and 312, respectively. Thus, it may be unnecessary to generate a bank selection signal for selecting any one of the first and second memory banks 311 and 312. In an embodiment, a point in time when the row/column address ADDR_R/ADDR_C is inputted to the first and second memory banks 311 and 312 may be a point in time when a MAC command (i.e., the MAC arithmetic signal MAC) requesting a data read operation for the first and second memory banks 311 and 312 for the MAC arithmetic operation is generated.

The MAC command generator 370 may output the MAC command signal MAC_CMD in response to the internal command signal I_CMD outputted from the command decoder 350. As illustrated in FIG. 16 , the MAC command signal MAC_CMD outputted from the MAC command generator 370 may include first to fifth MAC command signals. In an embodiment, the first MAC command signal may be a MAC active signal RACTV, the second MAC command signal may be a MAC read signal MAC_RD_BK, the third MAC command signal may be a MAC input latch signal MAC_L1, the fourth MAC command signal may be a MAC output latch signal MAC_L3, and the fifth MAC command signal may be a MAC result latch signal MAC_L_RST.

The MAC active signal RACTV may be generated based on the memory active signal ACT_M outputted from the command decoder 350. The MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may be sequentially generated based on the MAC arithmetic signal MAC outputted from the command decoder 350. That is, the MAC input latch signal MAC_L1 may be generated at a point in time when a certain time elapses from a point in time when the MAC read signal MAC_RD_BK is generated. The MAC output latch signal MAC_L3 may be generated at a point in time when a certain time elapses from a point in time when the MAC input latch signal MAC_L1 is generated. Finally, the MAC result latch signal MAC_L_RST may be generated based on the result read signal READ_RST outputted from the command decoder 350.

The MAC active signal RACTV outputted from the MAC command generator 370 may control an activation operation for the first and second memory banks 311 and 312. The MAC read signal MAC_RD_BK outputted from the MAC command generator 370 may control a data read operation for the first and second memory banks 311 and 312. The MAC input latch signal MAC_L1 outputted from the MAC command generator 370 may control an input data latch operation of the first MAC operator (MAC0) 320. The MAC output latch signal MAC_L3 outputted from the MAC command generator 370 may control an output data latch operation of the first MAC operator (MAC0) 320. The MAC result latch signal MAC_L_RST outputted from the MAC command generator 370 may control an output operation of MAC result data of the first MAC operator (MAC0) 320 and a reset operation of the first MAC operator (MAC0) 320.

As described above, in order to perform the deterministic MAC arithmetic operation of the PIM device 300, the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST outputted from the command decoder 350 may be sequentially generated at predetermined points in time (or clocks), respectively. Thus, the MAC active signal RACTV, the MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may also be generated and outputted from the MAC command generator 370 at predetermined points in time after the external command E_CMD is inputted to the PIM device 300, respectively. That is, a time period from a point in time when the first and second memory banks 311 and 312 are activated by the MAC active signal RACTV until a point in time when the first MAC operator (MAC0) 320 is reset by the MAC result latch signal MAC_L_RST may be predetermined.

FIG. 18 illustrates an example of a configuration of the MAC command generator 370 included in the PIM device 300 illustrated in FIG. 16 . Referring to FIG. 18 , the MAC command generator 370 may sequentially receive the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST from the command decoder 350. In addition, the MAC command generator 370 may sequentially generate and output the MAC active signal RACTV, the MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST. The MAC active signal RACTV, the MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may be outputted in series with certain time intervals.

In an embodiment, the MAC command generator 370 may be configured to include an active signal generator 371, a first delay circuit 372, and a second delay circuit 373. The active signal generator 371 may receive the memory active signal ACT_M to generate and output the MAC active signal RACTV. The MAC active signal RACTV outputted from the active signal generator 371 may be transmitted to the first and second memory banks 311 and 312 to activate the first and second memory banks 311 and 312. The MAC command generator 370 may receive the MAC arithmetic signal MAC outputted from the command decoder 350 to output the MAC arithmetic signal MAC as the MAC read signal MAC_RD_BK. The first delay circuit 372 may receive the MAC arithmetic signal MAC and may delay the MAC arithmetic signal MAC by a first delay time DELAY_T1 to generate and output the MAC input latch signal MAC_L1. The second delay circuit 373 may receive an output signal of the first delay circuit 372 and may delay the output signal of the first delay circuit 372 by a second delay time DELAY_T2 to generate and output the MAC output latch signal MAC_L3. The MAC command generator 370 may generate the MAC result latch signal MAC_L_RST in response to the result read signal READ_RST outputted from the command decoder 350.

The MAC command generator 370 may generate and output the MAC active signal RACTV in response to the memory active signal ACT_M outputted from the command decoder 350. Subsequently, the MAC command generator 370 may generate and output the MAC read signal MAC_RD_BK in response to the MAC arithmetic signal MAC outputted from the command decoder 350. The MAC arithmetic signal MAC may be inputted to the first delay circuit 372. The MAC command generator 370 may delay the MAC arithmetic signal MAC by a certain time determined by the first delay circuit 372 to generate and output an output signal of the first delay circuit 372 as the MAC input latch signal MAC_L1. The output signal of the first delay circuit 372 may be inputted to the second delay circuit 373. The MAC command generator 370 may delay the MAC input latch signal MAC_L1 by a certain time determined by the second delay circuit 373 to generate and output an output signal of the second delay circuit 373 as the MAC output latch signal MAC_L3. Subsequently, the MAC command generator 370 may generate and output the MAC result latch signal MAC_L_RST in response to the result read signal READ_RST outputted from the command decoder 350.

FIG. 19 illustrates input signals and output signals of the MAC command generator 370 illustrated in FIG. 18 with a timeline. In FIG. 19 , signals transmitted from the command decoder 350 to the MAC command generator 370 are illustrated in an upper dotted line box, and signals outputted from the MAC command generator 370 are illustrated in a lower dotted line box. Referring to FIGS. 18 and 19 , at a first point in time “T1” of the timeline, the memory active signal ACT_M may be inputted to the MAC command generator 370 and the MAC command generator 370 may output the MAC active signal RACTV. At a second point in time “T2” when a certain time, for example, a first latency L1 elapses from the first point in time “T1”, the MAC arithmetic signal MAC having a logic “high” level may be inputted to the MAC command generator 370. In response to the MAC arithmetic signal MAC having a logic “high” level, the MAC command generator 370 may output the MAC read signal MAC_RD_BK having a logic “high” level.

At a third point in time “T3” when a certain time elapses from the second point in time “T2”, a logic level of the MAC arithmetic signal MAC may change from a logic “high” level into a logic “low” level. At the third point in time “T3” when the first delay time DELAY_T1 elapses from the second point in time “T2”, the MAC command generator 370 may output the MAC input latch signal MAC_L1 having a logic “high” level. The first delay time DELAY_T1 may correspond to a delay time determined by the first delay circuit 372 illustrated in FIG. 18 . The first delay time DELAY_T1 may be set to be different according to a logic design scheme of the first delay circuit 372. In an embodiment, the first delay time DELAY_T1 may be set to be equal to or greater than a second latency L2. At a fourth point in time “T4” when a certain time elapses from the third point in time “T3”, the MAC command generator 370 may output the MAC output latch signal MAC_L3 having a logic “high” level. The fourth point in time “T4” may be a moment when the second delay time DELAY_T2 elapses from the third point in time “T3”. The second delay time DELAY_T2 may correspond to a delay time determined by the second delay circuit 373 illustrated in FIG. 18 . The second delay time DELAY_T2 may be set to be different according to a logic design scheme of the second delay circuit 373. In an embodiment, the second delay time DELAY_T2 may be set to be equal to or greater than a third latency L3. At a fifth point in time “T5” when a certain time, for example, a fourth L4 elapses from the fourth point in time “T4”, the result read signal READ_RST having a logic “high” level may be inputted to the MAC command generator 370. In response to the result read signal READ_RST having a logic “high” level, the MAC command generator 370 may output the MAC result latch signal MAC_L_RST having a logic “high” level, as described with reference to FIG. 18 .

In order to perform the deterministic MAC arithmetic operation, moments when the internal command signals ACT_M, MAC, and READ_RST generated by the command decoder 350 are inputted to the MAC command generator 370 may be fixed and moments when the MAC command signals RACTV, MAC_RD_BK, MAC_L1, MAC_L3, and MAC_L_RST are outputted from the MAC command generator 370 in response to the internal command signals ACT_M, MAC, and READ_RST may also be fixed. Thus, all of the first latency L1 between the first point in time “T1” and the second point in time “T2”, the second latency L2 between the second point in time “T2” and the third point in time “T3”, the third latency L3 between the third point in time “T3” and the fourth point in time “T4”, and the fourth latency L4 between the fourth point in time “T4” and the fifth point in time “T5” may have fixed values.

In an embodiment, the first latency L1 may be defined as a time it takes to activate both of the first and second memory banks based on the MAC active signal RACTV. The second latency L2 may be defined as a time it takes to read the first and second data out of the first and second memory banks (BK0 and BK1) 311 and 312 based on the MAC read signals MAC_RD_BK and to input the first and second data DA1 and DA2 into the first MAC operator (MAC0) 320. The third latency L3 may be defined as a time it takes to latch the first and second data DA1 and DA2 in the first MAC operator (MAC0) 320 based on the MAC input latch signals MAC_L1 and it takes the first MAC operator (MAC0) 320 to perform the MAC arithmetic operation of the first and second data. The fourth latency L4 may be defined as a time it takes to latch the output data in the first MAC operator (MAC0) 320 based on the MAC output latch signal MAC_L3.

FIG. 20 illustrates an example of a configuration of the first MAC operator (MAC0) 320 included in the PIM device 300 of FIG. 16 . The first MAC operator (MAC0) 320 included in the PIM device 300 may have the same configuration as the first MAC operator (MAC0) 220 described with reference to FIG. 7 except for a signal applied to clock terminals of first and second input latches 321-1 and 321-2 constituting a data input circuit 321. Thus, in FIG. 20 , the same reference numerals or the same reference symbols as used in FIG. 7 denote the same elements, and descriptions of the same elements as set forth with reference to FIG. 7 will be omitted hereinafter.

Describing in detail the differences between the first MAC operator (MAC0) 220 and the first MAC operator (MAC0) 320, in case of the first MAC operator (MAC0) 220 illustrated in FIG. 7 , the first input latch (221-1 of FIG. 7 ) and the second input latch (221-2 of FIG. 7 ) of the data input circuit (221 of FIG. 7 ) may be synchronized with the first and second MAC input latch signals MAC_L1 and MAC_L2, respectively, sequentially generated with a certain time interval to output the first data DA1 and the second data DA2. In contrast, in case of the first MAC operator (MAC0) 320, the MAC input latch signal MAC_L1 may be inputted to both of the clock terminals of the first and second input latches 321-1 and 321-2 constituting a data input circuit 321. Thus, both of the first and second input latches 321-1 and 321-2 may be synchronized with the MAC input latch signal MAC_L1 to output the first data DA1 and the second data DA2, respectively. Accordingly, the first MAC operator (MAC0) 320 may transmit the first and second data DA1 and DA2 to the MAC circuit 222 in parallel without any time interval between the first and second data DA1 and DA2. As a result, the MAC arithmetic operation of the MAC circuit 222 may be quickly performed without any delay of data input time.

FIGS. 21 to 25 are block diagrams illustrating operations of the PIM device 300 illustrated in FIG. 16 . In FIGS. 21 to 25 , the same reference numerals or the same reference symbols as used in FIG. 16 denote the same elements. First, referring to FIG. 21 , if the external command E_CMD requesting the MAC arithmetic operation and the input address I_ADDR are transmitted from an external device to the receiving driver 330, the receiving driver 330 may output the external command E_CMD and the input address I_ADDR to the command decoder 350 and the address latch 360, respectively. The command decoder 350 may decode the external command E_CMD to generate and transmit the memory active signal ACT_M to the MAC command generator 370. The MAC command generator 370 may generate and output the MAC active signal RACTV in response to the memory active signal ACT_M. The MAC active signal RACTV may be transmitted to the first memory bank (BK0) 311 and the second memory bank (BK1) 312. Both of the first memory bank (BK0) 311 and the second memory bank (BK1) 312 may be activated by the MAC active signal RACTV.

Next, referring to FIG. 22 , the command decoder 350 may generate and output the MAC arithmetic signal MAC having a logic “high(H)” level to the MAC command generator 370. In response to the MAC arithmetic signal MAC having a logic “high(H)” level, the MAC command generator 370 may generate and output the MAC read signal MAC_RD_BK having a logic “high(H)” level. The MAC read signal MAC_RD_BK having a logic “high(H)” level, together with the row/column address ADDR_R/ADDR_C, may be transmitted to the first memory bank (BK0) 311 and the second memory bank (BK1) 312. The first data DA1 may be read out of the first memory bank (BK0) 311 by the MAC read signal MAC_RD_BK having a logic “high(H)” level and may be transmitted to the first MAC operator (MAC0) 320 through the first BIO line 391. In addition, the second data DA2 may be read out of the second memory bank (BK1) 312 by the MAC read signal MAC_RD_BK having a logic “high(H)” level and may be transmitted to the first MAC operator (MAC0) 320 through the second BIO line 392.

Next, referring to FIG. 23 , a logic level of the MAC arithmetic signal MAC outputted from the command decoder 350 may change from a logic “high(H)” level into a logic “low(L)” level at a point in time when the first delay time DELAY_T1 determined by the first delay circuit (372 of FIG. 18 ) elapses from a point in time when the MAC read signal MAC_RD_BK is outputted from the MAC command generator 370. The MAC command generator 370 may generate and output the MAC input latch signal MAC_L1 having a logic “high(H)” level in response to the MAC arithmetic signal MAC having a logic “low(L)” level. The MAC input latch signal MAC_L1 having a logic “high(H)” level may be transmitted to the first MAC operator (MAC0) 320. The first MAC operator (MAC0) 320 may be synchronized with the MAC input latch signal MAC_L1 having a logic “high(H)” level to perform a latch operation of the first and second data DA1 and DA2 outputted from the first and second memory banks (BK0 and BK1) 311 and 312. If the latch operation of the first and second data DA1 and DA2 terminates, the first MAC operator (MAC0) 320 may perform the MAC arithmetic operation and may generate the MAC result data DA_MAC. The MAC result data DA_MAC generated by the first MAC operator (MAC0) 320 may be inputted to the output latch (223-1 of FIG. 20 ) included in the first MAC operator (MAC0) 320.

Next, referring to FIG. 24 , a logic level of the MAC arithmetic signal MAC outputted from the command decoder 350 may change from a logic “low(L)” level into a logic “high(H)” level at a point in time when the second delay time DELAY_T2 determined by the second delay circuit (373 of FIG. 18 ) elapses from a point in time when the MAC input latch signal MAC_L1 having a logic “high(H)” level is outputted from the MAC command generator 370. The MAC command generator 370 may generate and output the MAC output latch signal MAC_L3 having a logic “high(H)” level in response to the MAC arithmetic signal MAC having a logic “high(H)” level. The MAC output latch signal MAC_L3 having a logic “high(H)” level may be transmitted to the first MAC operator (MAC0) 320. The output latch (223-1 of FIG. 20 ) included in the first MAC operator (MAC0) 320 may be synchronized with the MAC output latch signal MAC_L3 having a logic “high(H)” level to transfer the MAC result data DA_MAC generated by the MAC circuit (222 of FIG. 20 ) to the transfer gate (223-2 of FIG. 20 ) included in the first MAC operator (MAC0) 320. The MAC result data DA_MAC outputted from the output latch (223-1 of FIG. 20 ) may be fed back to the addition logic circuit (222-2 of FIG. 20 ) for the accumulative adding calculation executed by the MAC circuit (222 of FIG. 20 ).

Next, referring to FIG. 25 , the command decoder 350 may output and transmit the result read signal READ_RST having a logic “high(H)” level to the MAC command generator 370. The MAC command generator 370 may generate and output the MAC result latch signal MAC_L_RST having a logic “high” level in response to the result read signal READ_RST having a logic “high(H)” level. The MAC result latch signal MAC_L_RST having a logic “high” level may be transmitted to the first MAC operator (MAC0) 320. As described with reference to FIG. 20 , the first MAC operator (MAC0) 320 may output the MAC result data DA_MAC to the GIO line 390 in response to the MAC result latch signal MAC_L_RST having a logic “high” level and may also reset the output latch (223-1 of FIG. 20 ) included in the first MAC operator (MAC0) 320 in response to the MAC result latch signal MAC_L_RST having a logic “high” level. The MAC result data DA_MAC transmitted to the GIO line 390 may be outputted to an external device through the serializer/deserializer 380 and the data I/O line 340. Although not shown in the drawings, the MAC result data DA_MAC outputted from the first MAC operator (MAC0) 320 may be written into the first memory bank (BK0) 311 through the first BIO line 391 without using the GIO line 390 or may be written into the second memory bank (BK1) 312 through the second BIO line 392 without using the GIO line 390.

FIG. 26 is a timing diagram illustrating an operation of the PIM device 300 illustrated in FIG. 16 . Referring to FIG. 26 , at a first point in time “T1”, the MAC command generator 370 may be synchronized with a falling edge of a clock signal CLK to generate and output the MAC read signal MAC_RD_BK (R) having a logic “high(H)” level. The first and second memory banks (BK0 and BK1) 311 and 312 may be selected by the MAC read signal MAC_RD_BK (R) having a logic “high(H)” level so that the first data DA1 and the second data DA2 are read out of the first and second memory banks (BK0 and BK1) 311 and 312. If a certain time elapses from a point in time when first data DA1 and the second data DA2 are read out, the first MAC operator (MAC0) 320 may perform the MAC arithmetic operation of the first and second data DA1 and DA2 to generate the MAC result data DA_MAC. At a second point in time “T2”, the MAC command generator 370 may be synchronized with a falling edge of the clock signal CLK to generate and output the MAC result latch signal MAC_L_RST (RST) having a logic “high” level. The MAC result data DA_MAC may be transmitted to the GIO line 390 by the MAC result latch signal MAC_L_RST (RST) having a logic “high” level.

FIG. 27 illustrates a disposal structure indicating placement of memory banks and MAC operators included in a PIM device 400 according to another embodiment of the present disclosure. Referring to FIG. 27 , the PIM device 400 may include memory devices such as a plurality of memory banks (e.g., first to sixteenth memory banks BK0, . . . , and BK15), processing devices such as a plurality of MAC operators (e.g., first to sixteenth MAC operators MAC0, . . . , and MAC15), and a global buffer GB. A core circuit may be disposed to be adjacent to the memory banks BK0, . . . , and BK15. The core circuit may include X-decoders XDECs and Y-decoders/IO circuits YDEC/IOs. The memory banks BK0, . . . , and BK15 and the core circuit may have the same configuration as described with reference to FIG. 2 . Thus, descriptions of the memory banks BK0, . . . , and BK15 and the core circuit will be omitted hereinafter. The MAC operators MAC0, . . . , and MAC15 may be disposed to be allocated to the memory banks BK0, . . . , and BK15, respectively. That is, in the PIM device 400, two or more memory banks do not share one MAC operator with each other. Thus, the number of the MAC operators MAC0, . . . , and MAC15 included in the PIM device 400 may be equal to the number of the memory banks BK0, . . . , and BK15 included in the PIM device 400. One of the memory banks BK0, . . . , and BK15 together with one of the MAC operators MAC0, . . . , and MAC15 may constitute one MAC unit. For example, the first memory bank BK0 and the first MAC operator MAC0 may constitute a first MAC unit, and the second memory bank BK1 and the second MAC operator MAC1 may constitute a second MAC unit. Similarly, the sixteenth memory bank BK15 and the sixteenth MAC operator MAC15 may constitute a sixteenth MAC unit. In each of the first to sixteenth MAC units, the MAC operator may receive first data DA1 to be used for the MAC arithmetic operation from the respective memory bank.

The PIM device 400 may further include a peripheral circuit PERI. The peripheral circuit PERI may be disposed in a region other than an area in which the memory banks BK0, BK1, . . . , and BK15; the MAC operators MAC0, . . . , and MAC15; and the core circuit are disposed. The peripheral circuit PERI may be configured to include a control circuit relating to a command/address signal, a control circuit relating to input/output of data, and a power supply circuit. The peripheral circuit PERI of the PIM device 400 may have substantially the same configuration as the peripheral circuit PERI of the PIM device 100 illustrated in FIG. 2 . A difference between the peripheral circuit PERI of the PIM device 400 and the peripheral circuit PERI of the PIM device 100 is that the global buffer GB is disposed in the peripheral circuit PERI of the PIM device 400. The global buffer GB may receive second data DA2 to be used for the MAC operation from an external device and may store the second data DA2. The global buffer GB may output the second data DA2 to each of the MAC operators MAC0, . . . , and MAC15 through a GIO line. In the event that the PIM device 400 performs neural network calculation, for example, an arithmetic operation in a deep learning process, the first data DA1 may be weight data and the second data DA2 may be vector data.

The PIM device 400 according to the present embodiment may operate in a memory mode or a MAC arithmetic mode. In the memory mode, the PIM device 400 may operate to perform the same operations as general memory devices. The memory mode may include a memory read operation mode and a memory write operation mode. In the memory read operation mode, the PIM device 400 may perform a read operation for reading out data from the memory banks BK0, BK1, . . . , and BK15 to output the read data, in response to an external request. In the memory write operation mode, the PIM device 400 may perform a write operation for storing data provided by an external device into the memory banks BK0, BK1, . . . , and BK15, in response to an external request. In the MAC arithmetic mode, the PIM device 400 may perform the MAC arithmetic operation using the MAC operators MAC0, . . . , and MAC15. In the PIM device 400, the MAC arithmetic operation may be performed in a deterministic way, and the deterministic MAC arithmetic operation of the PIM device 400 will be described more fully hereinafter. Specifically, the PIM device 400 may perform the read operation of the first data DA1 for each of the memory banks BK0, . . . , and BK15 and the read operation of the second data DA2 for the global buffer GB, for the MAC arithmetic operation in the MAC arithmetic mode. In addition, each of the MAC operators MAC0, . . . , and MAC15 may perform the MAC arithmetic operation of the first data DA1 and the second data DA2 to store a result of the MAC arithmetic operation into the memory bank or to output the result of the MAC arithmetic operation to an external device. In some cases, the PIM device 400 may perform a data write operation for storing data to be used for the MAC arithmetic operation into the memory banks before the data read operation for the MAC arithmetic operation is performed in the MAC arithmetic mode.

The operation mode of the PIM device 400 according to the present embodiment may be determined by a command which is transmitted from a host or a controller to the PIM device 400. In an embodiment, if a first external command requesting a read operation or a write operation for the memory banks BK0, BK1, . . . , and BK15 is transmitted from the host or the controller to the PIM device 400, the PIM device 400 may perform the data read operation or the data write operation in the memory mode. Alternatively, if a second external command requesting the MAC arithmetic operation is transmitted from the host or the controller to the PIM device 400, the PIM device 400 may perform the data read operation and the MAC arithmetic operation.

The PIM device 400 may perform the deterministic MAC arithmetic operation. Thus, the host or the controller may always predict a point in time (or a clock) when the MAC arithmetic operation terminates in the PIM device 400 from a point in time when an external command requesting the MAC arithmetic operation is transmitted from the host or the controller to the PIM device 400. Because the timing is predictable, no operation for informing the host or the controller of a status of the MAC arithmetic operation is required while the PIM device 400 performs the deterministic MAC arithmetic operation. In an embodiment, a latency during which the MAC arithmetic operation is performed in the PIM device 400 may be set to a fixed value for the deterministic MAC arithmetic operation.

FIG. 28 is a block diagram illustrating an example of a detailed configuration of a PIM device 500 corresponding to the PIM device 400 illustrated in FIG. 27 . FIG. 28 illustrates only a first memory bank (BK0) 511 and a first MAC operator (MAC0) 520 constituting a first MAC unit among a plurality of MAC units. However, FIG. 28 illustrates merely an example for simplification of the drawing. Accordingly, the following description for the first MAC unit may be equally applicable to the remaining MAC units. Referring to FIG. 28 , the PIM device 500 may be configured to include the first memory bank (BK0) 511 and the first MAC operator (MAC0) 520 constituting the first MAC unit as well as a global buffer 595. The PIM device 500 may further include a GIO line 590 and a BIO line 591 used as data transmission lines. The first memory bank (BK0) 511 and the first MAC operator (MAC0) 520 may communicate with the global buffer 595 through the GIO line 590. Only the data transmission between the first memory bank (BK0) 511 and the first MAC operator (MAC0) 520 may be achieved through the BIO line 591. The BIO line 591 is dedicated specifically for data transmission between the first memory bank (BK0) 511 and the first MAC operator (MAC0) 520. Thus, the first MAC operator (MAC0) 520 may receive the first data DA1 to be used for the MAC arithmetic operation from the first memory bank (BK0) 511 through the BIO line 591 and may receive the second data DA2 to be used for the MAC arithmetic operation from the global buffer 595 through the GIO line 590.

The PIM device 500 may include a receiving driver (RX) 530, a data I/O circuit (DQ) 540, a command decoder 550, an address latch 560, a MAC command generator 570, and a serializer/deserializer (SER/DES) 580. The command decoder 550, the address latch 560, the MAC command generator 570, and the serializer/deserializer 580 may be disposed in the peripheral circuit PERI of the PIM device 400 illustrated in FIG. 27 . The receiving driver 530 may receive an external command E_CMD and an input address I_ADDR from an external device. The external device may denote a host or a controller coupled to the PIM device 500. Hereinafter, it may be assumed that the external command E_CMD transmitted to the PIM device 500 is a command requesting the MAC arithmetic operation. That is, the PIM device 500 may perform the deterministic MAC arithmetic operation in response to the external command E_CMD. The data I/O circuit 540 may provide a means through which the PIM device 500 communicates with the external device.

The receiving driver 530 may separately output the external command E_CMD and the input address I_ADDR received from the external device. Data DA inputted to the PIM device 500 through the data I/O circuit 540 may be processed by the serializer/deserializer 580 and may be transmitted to the first memory bank (BK0) 511 and the global buffer 595 through the GIO line 590 of the PIM device 500. The data DA outputted from the first memory bank (BK0) 511 and the first MAC operator (MAC0) 520 through the GIO line 590 may be processed by the serializer/deserializer 580 and may be outputted to the external device through the data I/O circuit 540. The serializer/deserializer 580 may convert the data DA into parallel data if the data DA are serial data or may convert the data DA into serial data if the data DA are parallel data. For the data conversion, the serializer/deserializer 580 may include a serializer converting parallel data into serial data and a deserializer converting serial data into parallel data.

The command decoder 550 may decode the external command E_CMD outputted from the receiving driver 530 to generate and output the internal command signal I_CMD. The internal command signal I_CMD outputted from the command decoder 550 may be the same as the internal command signal I_CMD described with reference to FIG. 17 . That is, the internal command signal I_CMD may include a first internal command signal corresponding to the memory active signal ACT_M, a second internal command signal corresponding to the MAC arithmetic signal MAC, and a third internal command signal corresponding to the result read signal READ_RST. The first to third internal command signals outputted from the command decoder 550 may be sequentially inputted to the MAC command generator 570. As described with reference to FIG. 17 , the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST outputted from the command decoder 550 may be sequentially generated at predetermined points in time (or clocks) in order to perform the deterministic MAC arithmetic operation of the PIM device 500. Thus, the host or the controller outputting the external command E_CMD may predict the points in time when the first to third internal command signals constituting the internal command signal I_CMD are generated by the command decoder 550 in advance at a point in time when the external command E_CMD is outputted from the host or the controller. That is, the host or the controller may predict a point in time (or a clock) when the MAC arithmetic operation terminates in the PIM device 500 after the external command E_CMD requesting the MAC arithmetic operation is transmitted from the host or the controller to the PIM device 500, even without receiving any signals from the PIM device 500.

The address latch 560 may convert the input address I_ADDR outputted from the receiving driver 530 into a row/column address ADDR_R/ADDR_C to output the row/column address ADDR_R/ADDR_C. The row/column address ADDR_R/ADDR_C outputted from the address latch 560 may be transmitted to the first memory bank (BK0) 511. According to the present embodiment, the first data and the second data to be used for the MAC arithmetic operation may be simultaneously read out of the first memory bank (BK0) 511 and the global buffer 595, respectively. Thus, it may be unnecessary to generate a bank selection signal for selecting the first memory bank 511. A point in time when the row/column address ADDR_R/ADDR_C is inputted to the first memory bank 511 may be a point in time when a MAC command (i.e., the MAC arithmetic signal MAC) requesting a data read operation for the first memory bank 511 for the MAC arithmetic operation is generated.

The MAC command generator 570 may output the MAC command signal MAC_CMD in response to the internal command signal I_CMD outputted from the command decoder 550. The MAC command signal MAC_CMD outputted from the MAC command generator 570 may be the same as the MAC command signal MAC_CMD described with reference to FIG. 17 . That is, the MAC command signal MAC_CMD outputted from the MAC command generator 570 may include the MAC active signal RACTV corresponding to the first MAC command signal, the MAC read signal MAC_RD_BK corresponding to the second MAC command signal, the MAC input latch signal MAC_L1 corresponding to the third MAC command signal, the MAC output latch signal MAC_L3 corresponding to the fourth MAC command signal, and the MAC result latch signal MAC_L_RST corresponding to the fifth MAC command signal.

The MAC active signal RACTV may be generated based on the memory active signal ACT_M outputted from the command decoder 550. The MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may be sequentially generated based on the MAC arithmetic signal MAC outputted from the command decoder 550. That is, the MAC input latch signal MAC_L1 may be generated at a point in time when a certain time elapses from a point in time when the MAC read signal MAC_RD_BK is generated. The MAC output latch signal MAC_L3 may be generated at a point in time when a certain time elapses from a point in time when the MAC input latch signal MAC_L1 is generated. Finally, the MAC result latch signal MAC_L_RST may be generated based on the result read signal READ_RST outputted from the command decoder 550.

The MAC active signal RACTV outputted from the MAC command generator 570 may control an activation operation for the first memory bank 511. The MAC read signal MAC_RD_BK outputted from the MAC command generator 570 may control a data read operation for the first memory bank 511 and the global buffer 595. The MAC input latch signal MAC_L1 outputted from the MAC command generator 570 may control an input data latch operation of the first MAC operator (MAC0) 520. The MAC output latch signal MAC_L3 outputted from the MAC command generator 570 may control an output data latch operation of the first MAC operator (MAC0) 520. The MAC result latch signal MAC_L_RST outputted from the MAC command generator 570 may control an output operation of MAC result data of the first MAC operator (MAC0) 520 and a reset operation of the first MAC operator (MAC0) 520.

As described above, in order to perform the deterministic MAC arithmetic operation of the PIM device 500, the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST outputted from the command decoder 550 may be sequentially generated at predetermined points in time (or clocks), respectively. Thus, the MAC active signal RACTV, the MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may also be generated and outputted from the MAC command generator 570 at predetermined points in time after the external command E_CMD is inputted to the PIM device 500, respectively. That is, a time period from a point in time when the first and second memory banks 511 is activated by the MAC active signal RACTV until a point in time when the first MAC operator (MAC0) 520 is reset by the MAC result latch signal MAC_L_RST may be predetermined.

The MAC command generator 570 of the PIM device 500 according to the present embodiment may have the same configuration as described with reference to FIG. 18 . In addition, the input signals and the output signals of the MAC command generator 570 may be inputted to and outputted from the MAC command generator 570 at the same points in time as described with reference to FIG. 19 . As described with reference to FIGS. 18 and 19 , the MAC command generator 570 may sequentially receive the memory active signal ACT_M, the MAC arithmetic signal MAC, and the result read signal READ_RST from the command decoder 550. In addition, the MAC command generator 570 may sequentially generate and output the MAC active signal RACTV, the MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST. The MAC active signal RACTV, the MAC read signal MAC_RD_BK, the MAC input latch signal MAC_L1, the MAC output latch signal MAC_L3, and the MAC result latch signal MAC_L_RST may be outputted from the MAC command generator 570 in series with certain time intervals.

The MAC command generator 570 may generate and output the MAC active signal RACTV in response to the memory active signal ACT_M outputted from the command decoder 550. Subsequently, the MAC command generator 570 may generate and output the MAC read signal MAC_RD_BK in response to the MAC arithmetic signal MAC outputted from the command decoder 550. The MAC command generator 570 may delay the MAC arithmetic signal MAC by a certain time determined by the first delay circuit (372 of FIG. 18 ) to generate and output the MAC input latch signal MAC_L1. The MAC command generator 570 may delay the MAC input latch signal MAC_L1 by a certain time determined by the second delay circuit (373 of FIG. 18 ) to generate and output the MAC output latch signal MAC_L3. Subsequently, the MAC command generator 570 may generate and output the MAC result latch signal MAC_L_RST in response to the result read signal READ_RST outputted from the command decoder 550.

FIG. 29 is a block diagram illustrating an operation of the PIM device 500 illustrated in FIG. 28 . In FIG. 29 , the same reference numerals or the same reference symbols as used in FIG. 16 denote the same elements. The operation of the PIM device 500 according to the present embodiment may be similar to the operation of the PIM device 300 described with reference to FIG. 16 except a transmission process of the first and second data DA1 and DA2 inputted to the first MAC operator (MAC0) 520. Thus, the operation of the PIM device 500 executed before the first and second data DA1 and DA2 are transmitted to the first MAC operator (MAC0) 520 may be the same as the operation of the PIM device 300 described with reference to FIG. 21 . As illustrated in FIG. 29 , when the MAC arithmetic signal MAC having a logic “high(H)” level is transmitted from the command decoder 550 to the MAC command generator 570, the MAC command generator 570 may generate and output the MAC read signal MAC_RD_BK having a logic “high(H)” level. The MAC read signal MAC_RD_BK having a logic “high(H)” level, together with the row/column address ADDR_R/ADDR_C, may be transmitted to the first memory bank (BK0) 511. In such a case, a global buffer read signal B_R may also be transmitted to the global buffer 595. The first data DA1 may be read out of the first memory bank (BK0) 511 by the MAC read signal MAC_RD_BK having a logic “high(H)” level and may be transmitted to the first MAC operator (MAC0) 520 through the BIO line 591. In addition, the second data DA2 may be read out of the global buffer 595 by the global buffer read signal B_R and may be transmitted to the first MAC operator (MAC0) 520 through the GIO line 590. The operation of the PIM device 500 executed after the first and second data DA1 and DA2 are transmitted to the first MAC operator (MAC0) 520 may be the same as the operation of the PIM device 300 described with reference to FIGS. 23 to 25 .

FIG. 30 is a timing diagram illustrating an operation of the PIM device 500 illustrate in FIG. 28 . Referring to FIG. 30 , at a first point in time “T1”, the MAC command generator 570 may be synchronized with a falling edge of a clock signal CLK to generate and output the MAC read signal MAC_RD_BK (R) having a logic “high(H)” level. The first memory bank (BK0) 511 may be selected by the MAC read signal MAC_RD_BK (R) having a logic “high(H)” level so that the first data DA1 are read out of the first memory bank (BK0) 511. In addition, the second data DA2 may be read out of the global buffer 595. If a certain time elapses from a point in time when the first and second data DA1 and DA2 are read out of the first memory bank (BK0) 511 and the global buffer 595, the first MAC operator (MAC0) 520 may perform the MAC arithmetic operation of the first and second data DA1 and DA2 to generate the MAC result data DA_MAC. At a second point in time “T2”, the MAC command generator 570 may be synchronized with a falling edge of the clock signal CLK to generate and output the MAC result latch signal MAC_L_RST (RST). The MAC result data DA_MAC may be transmitted to an external device through the GIO line 590 or to the first memory bank (BK0) 511 through the BIO line 591, by the MAC result latch signal MAC_L_RST (RST).

FIG. 31 is a block diagram illustrating a PIM device 600 according to another embodiment of the present disclosure. Referring to FIG. 31 , the PIM device 600 may include first to “K”^(th) (“K” is a natural number) memory banks BK0-BK“K−1”, a global buffer GB, first to “K”^(th) processing elements PE0-PE“K−1”, a command decoder 610, an address decoder 620, a data input/output circuit 630, and a processor unit 640. In addition, the PIM device 600 may include a global input/output (GIO) line and a vector transmission line as transmission lines. Although omitted from FIG. 31 , the PIM device 600 may also include a signal transmission line for transmitting control signals and internal instructions.

The first to “K”^(th) memory banks BK0-BK“K−1” and the first to “K”^(th) processing elements PE0-PE“K−1” may constitute first to “K”^(th) processing units PU0-PU“K−1”, respectively. That is, one processing unit, for example, the “J”^(th) (“J” is a natural number from 1 to “K”) processing unit PU“J” among the first to “K”^(th) processing units PU0-PU“K−1” may include the “J”^(th) memory bank BK“J−1” and the “J”^(th) processing element PE“J−1”. As exemplified in FIG. 31 , the first processing unit PU0 may include the first memory bank BK0 and the first processing element PE0. The second processing unit PU1 may include the second memory bank BK1 and the second processing element PE1. The third processing unit PU2 may include the third memory bank BK2 and the third processing element PE2. The fourth processing unit PU3 may include the fourth memory bank BK3 and the fourth processing element PE3. The “K−1”^(th) processing unit PU“K−2” may include the “K−1”^(th) memory bank BK“K−2” and the “K−1”^(th) processing element PE“K−2”. The “K”^(th) processing unit PU“K−1” may include the “K”^(th) memory bank BK“K−1” and the “K”^(th) processing element PE“K−1”.

The PIM device 600 may operate in a normal mode (or a memory mode) or in an accelerator mode (or an arithmetic mode). In the normal mode, the PIM device 600 may perform a read operation and a write operation on the first to “K”^(th) memory banks BK0-BK“K−1”. Specifically, when the PIM device 600 is in the normal mode, the first to “K”^(th) memory banks BK0-BK“K−1” may transmit data designated by a bank address BA/row address RA/column address CA to the GIO line in response to a read control signal RD. The data that is transmitted to the GIO line may be output from the PIM device 600 through the data input/output circuit 630. When the PIM device 600 is in the normal mode, the first to “K”^(th) memory banks BK0-BK“K−1” may store the data that is transmitted through the GIO line in a location designated by an address in response to a write control signal WT. While the PIM device 600 is in the normal mode, the data stored in the first to “K”^(th) memory banks BK0-BK“K−1” may be data that is read while the PIM device 600 operates in the normal mode, or may be data that is used for arithmetic operation while the PIM device 600 operates in the accelerator mode.

In the normal mode, the PIM device 600 may set operation instruction sets that define arithmetic operations to be performed by the PIM device 600 in the accelerator mode. Specifically, in the normal mode, the PIM device 600 may receive a plurality of operation instruction sets from a host or a controller. In an example, the operation instruction sets may be transmitted in data format. The operation instruction sets transmitted to the PIM device 600 may be transmitted to the processor unit 641 through the data input/output circuit 630 and the GIO line. The processor unit 641 may transmit the operation instruction sets to the first to “K”^(th) processing elements PE0-PE“K−1”. The operation instruction sets transmitted to the first to “K”^(th) processing elements PE0-PE“K−1” may control the arithmetic operations in the first to “K”^(th) processing elements PE0-PE“K−1” while the PIM device 600 operates in the accelerator mode.

The PIM device 600 may operate in the accelerator mode in response to transmission of an accelerator mode start signal START from a host or a controller. When the PIM device 600 operates in the accelerator mode, particularly when the PIM device 600 performs a MAC arithmetic operation, the first to “K”^(th) memory banks BK0-BK“K−1” may perform a first data providing operation. The first data are provided from the first to “K”^(th) memory banks BK0-BK“K−1” to the first to “K”^(th) processing elements PE0-PE“K−1” by the first data providing operation. In an example, the first data may be divided into first to “K”^(th) groups. In this case, the first to “K”^(th) memory banks BK0-BK“K−1” may provide the first to “K”^(th) groups of the first data to the first to “K”^(th) processing elements PE0-PE“K−1”, respectively. For example, the “J”^(th) (“J” is one of 1 to “K”) memory bank BK“J−1” may provide the “J”^(th) group of the first data to the “J”^(th) processing element PE“J−1”. Specifically, the first memory bank BK0 may provide the first group of the first data to the first processing element PE0. The second memory bank BK1 may provide the second group of the first data to the second processing element PE1. The remaining memory banks may also provide the first data to the remaining processing elements in a group unit in the same manner. In an example, the first data may be elements of a weight matrix used in the MAC arithmetic operation or the vector operation, that is, the weight data. When each of the first to “K”^(th) processing elements PE0-PE“K−1” includes first to “L”^(th) (“L” is a natural number) MAC operators, each of the first to “K”^(th) groups of the first data may include first to “L”^(th) sets. That is, the first group of the first data may include first to “L”^(th) sets. The second group of the first data may also include first to “L”^(th) sets. The number of sets (i.e., “L”) of each of the first to “K”^(th) groups of the first data may be the same as the number of MAC operators included in each of the first to “K”^(th) processing elements PE0-PE“K−1”.

When the PIM device 600 operates in the accelerator mode, particularly, when the PIM device 600 performs a MAC arithmetic operation, the global buffer GB may provide the second data used for the MAC arithmetic operation to the first to “K”^(th) processing elements PE0-PE“K−1”. The transmission of the second data from the global buffer GB to the first to “K”^(th) processing elements PE0-PE“K−1” may be performed through a vector transmission line. In an example, data transmission capacity of the vector transmission line is at least “L” times greater than data transfer capacity of the GIO line. In an example, the second data may include first to “L”^(th) sets. When each of the first to “K”^(th) processing elements PE0-PE“K−1” includes the first to “L”^(th) MAC operators, the global buffer GB may provide the first to “L”^(th) sets of the second data to the first to “K”^(th) processing elements PE0-PE“K−1”. In an example, the second data may be elements of a vector matrix used for a MAC arithmetic operation or a vector operation, that is, vector data.

The first to “K”^(th) processing elements PE0-PE“K−1” may receive the first data and the second data from the first to “K”^(th) memory banks BK0-BK“K−1” and the global buffer GB, respectively. When each of the first to “K”^(th) processing elements PE0-PE“K−1” includes the first to “L”^(th) MAC operators, each of the first to “K”^(th) processing elements PE0-PE“K−1” may be provided with the first to “K”^(th) groups of the first data from the first to “K”^(th) memory banks BK0-BK“K−1”, respectively. The first to “K”^(th) processing elements PE0-PE“K−1” may be commonly provided with the first to “L”^(th) sets of the second data from the global buffer GB. The first to “K”^(th) processing elements PE0-PE“K−1” may perform arithmetic operations using the first to “K”^(th) groups of the first data and the first to “L”^(th) sets of the second data. That is, the “J”^(th) processing element PE“J−1” may perform a MAC arithmetic operation using the “J”^(th) group of the first data that is transmitted from the “J”^(th) memory bank BK“J−1” and the first to “L”^(th) sets of the second data that are transmitted from the global buffer GB. Specifically, the first processing element PE0 may perform a MAC arithmetic operation using the first group of the first data that is provided from the first memory bank BK0 and the first to “L”^(th) sets of the second data that are provided from the global buffer GB. The second processing element PE1 may perform a MAC arithmetic operation using the second group of the first data that is provided from the second memory bank BK1 and the first to “L”^(th) sets of the second data that are provided from the global buffer GB. The third processing element PE2 may perform a MAC arithmetic operation using the third group of the first data that is provided from the third memory bank BK2 and the first to “L”^(th) sets of the second data that are provided from the global buffer GB. The remaining processing elements may perform MAC arithmetic operations in the same manner. The configuration of the first to “K”^(th) processing elements PE0-PE“K−1” will be described in more detail below.

The command decoder 610 may receive a command CMD and an accelerator mode start signal START from an external device, for example, a host or a controller. When the command CMD is transmitted from a host or a controller, the command decoder 610 may decode the command CMD to transmit a normal mode control signal, for example, a read control signal RD or a write control signal WT to the first to “K”^(th) memory banks BK0-BK“K−1”. In this case, the first to “K”^(th) memory banks BK0-BK“K−1” of the PIM device 600 may perform a normal mode operation, that is, a read operation or a write operation corresponding to a normal mode control signal that is output from the command decoder 610. When the accelerator mode start signal START is transmitted from a host or a controller, the command decoder 610 may transmit the accelerator mode start signal START to the first to “K”^(th) processing elements PE0-PE“K−1”. In this case, the PIM device 600 may perform an accelerator mode operation corresponding to an operation instruction set that is set in synchronization with the accelerator mode start signal START output from the command decoder 610.

The command decoder 610 may additionally output a refresh control signal REF. In an example, the refresh control signal REF may be output from the command decoder 610 in response to a refresh command from a host. In another example, although not illustrated in FIG. 31 , the refresh control signal REF may be generated in a refresh control circuit in the PIM device 600, and may be transmitted to the command decoder 610. When the PIM device 600 operates in the normal mode, the command decoder 610 may transmit the refresh control signal REF to the first to “K”^(th) memory banks BK0-BK“K−1”. On the other hand, when the PIM device 600 operates in the accelerator mode, the command decoder 610 may transmit the refresh control signal REF to the processor unit 640.

The address decoder 620 may receive an address ADDR from an external device. The address decoder 620 may decode (or latch) the address ADDR to output a row address RA, a bank address BA, and a column address CA. The address decoder 620 may transmit the bank address BA/row address RA/column address CA to the first to “K”^(th) memory banks BK0-BK“K−1”. In an example, when the global buffer GB stores the second data based on the column address CA, the address decoder 620 may transmit the column address CA to the global buffer GB.

The data input/output circuit 630 may perform a data input operation and a data output operation of the PIM device 600. The data input/output circuit 630 may transmit data that is transmitted from an external device to the first to “K”^(th) memory banks BK0-BK“K−1” and the global buffer GB through the GIO line. In addition, the data input/output circuit 630 may output data DATA that is transmitted through the GIO line from the first to “K”^(th) memory banks BK0-BK“K−1” and the first to “K”^(th) processing elements PE0-PE“K−1” to an external device.

The processor unit 640 may transmit operation instruction sets to the first to “K”^(th) processing elements PE0-PE“K−1” while the PIM device 600 performs a normal mode operation. The processor unit 640 may receive the accelerator mode start signal START and the refresh control signal REF from the command decoder 610. When the accelerator mode start signal START is transmitted from the command decoder 610 to the processor unit 640, the PIM device 600 may start to perform an accelerator mode operation. The processor unit 640 may transmit the accelerator mode start signal START to the first to “K”^(th) processing elements PE0-PE“K−1”. When the refresh control signal REF is transmitted from the command decoder 610, the processor unit 640 may transmit the refresh control signal REF to the first to “K”^(th) memory banks BK0-BK“K−1”.

The processor unit 640 may include a main processor 641 and an instruction buffer 642. The main processor 641 may output an operation instruction set OP_INS while the PIM device 600 operates in the normal mode. Specifically, while the PIM device 600 operates in the normal mode, the main processor 641 may transmit a request signal REQ for requesting transmission of the operation instruction set OP_INS to the command buffer 642, to the command buffer 642. The main processor 641 may transmit the operation instruction set OP_INS that is transmitted from the instruction buffer 642 to the first to “K”^(th) processing elements PE0-PE“K−1”. The main processor 642 may output the accelerator mode start signal START so that the PIM device 600 operates in the accelerator mode. Specifically, when the accelerator mode start signal START is transmitted from the command decoder 610, the main processor 641 may transmit the accelerator mode start signal START to the first to “K”^(th) processing elements PE0-PE“K−1”, after confirming that the operation in which the operation instruction set OP_INS stored in the instruction buffer 642 is transmitted to the first to “K”^(th) processing elements PE0-PE“K−1” is completed. As mentioned above, the first to “K”^(th) processing elements PE0-PE“K−1” may perform arithmetic operations controlled by the operation instruction set OP_INS in response to the accelerator mode start signal START.

FIG. 32 is a diagram illustrating an example of a configuration of the first processing element PE0 included in the PIM device 600 of FIG. 31 . The description of a first processing element PE0(1) according to the present example below may be equally applied to the second to “K”^(th) processing elements PE1-PE“K−1”. In this example, the first processing element PE0(1) includes first to fourth MAC operators, but this is only an example, and the first processing element PE0 may include five or more MAC operators.

Referring to FIG. 32 , the first processing element PE0(1) may include an internal instruction buffer 710, an internal processor 720, first to fourth MAC operators 731-734, and a vector engine 740. The first to fourth MAC operators 731-734 may perform a first arithmetic operation, for example, a MAC arithmetic operation. The vector engine 740 may perform a second arithmetic operation, for example, an operation of processing the vector data. In an example, the first processing element PE0(1) may include a plurality of vector engines. The internal instruction buffer 710 may store an operation instruction set OP_INS transmitted from the main processor (641 of FIG. 31 ). The operation instruction set OP_INS stored in the internal instruction buffer 710 may be updated by the main processor (641 of FIG. 31 ). The internal processor 720 may receive an accelerator mode start signal START from the main processor (641 of FIG. 31 ). When the accelerator mode start signal START is received, the internal processor 720 may generate an internal control signal IN_CTL that corresponds to the operation instruction set OP_INS stored in the internal instruction buffer 710 to transmit the internal control signal IN_CTL to the first to fourth MAC operators 731-734 and the vector engine 740. Although not illustrated in FIG. 32 , the internal processor 720 may directly receive an operation instruction set OP_INS that is different from the operation instruction set OP_INS stored in the internal instruction buffer 710 from the main processor (641 in FIG. 31 ). In this case, the internal processor 720 may generate an internal control signal IN_CTL corresponding to another operation instruction set OP_INS transmitted from the main processor (641 of FIG. 31 ), without referring to the operation instruction set OP_INS stored in the internal instruction buffer 710. When the arithmetic operations in the first to fourth MAC operators 731-734 and the vector engine 740 according to the operation instruction set OP_INS are finished, the internal processor 720 may generate and output an accelerator mode end signal DONE. The accelerator mode end signal DONE that is output from the internal processor 720 may be transmitted to the main processor (641 of FIG. 31 ).

The first to fourth MAC operators 731-734 may receive first data, that is, weight data from a first memory bank BK0 through a GIO line. In this example, the GIO line may be replaced with a BIO line. In this case, the description of the GIO line below may be equally applied to the BIO line. The first to fourth MAC operators 731-734 may receive second data, that is, vector data from a global buffer (GB in FIG. 31 ) through a vector transmission line. The first to fourth MAC operators 731-734 may receive the vector data from the vector engine 740 through the vector transmission line. The first to fourth MAC operators 731-734 may perform a MAC arithmetic operation defined by an internal control signal IN_CTL that is transmitted from the internal processor 720.

The vector engine 740 may receive the vector data from the global buffer (GB in FIG. 31 ) through the vector transmission line. The vector engine 740 may receive third data required for a vector arithmetic from the first memory bank BK0 through the GIO line. The vector engine 740 may use the vector data in response to the internal control signal IN_CTL transmitted from the internal processor 720, or may perform a vector arithmetic using the vector data and the third data. The vector engine 740 may perform an operation of processing the vector data in response to the internal control signal IN_CTL. The vector engine 740 may transmit result data of the vector arithmetic or the processed data for the vector data to the first to fourth MAC operators 731-734 through the vector transmission line.

FIG. 33 is a diagram illustrating another example of a configuration of the first processing element PE0 included in the PIM device 600 of FIG. 31 . The description of the first processing element PE0(2) according to the present example may be equally applied to the second to “K”^(th) processing elements PE1-PE“K−1”. In FIG. 33 , the same reference numerals as those of FIG. 32 indicate the same components, and accordingly, descriptions of contents overlapping with those described with reference to FIG. 32 below will be omitted.

Referring to FIG. 33 , the first processing element PE0(2) may include a first buffer 751, a second buffer 752, and a third buffer 753. The first buffer 751 may be coupled to a GIO line. Accordingly, the first buffer 751 may store weight data transmitted from an external device, for example, a host or a controller through a data input/output circuit (630 in FIG. 31 ) and the GIO line, by the control operation of a main processor (641 in FIG. 31 ). In addition, the first buffer 751 may store weight data transmitted from first to “K”^(th) memory banks BK0-BK“K−1” through the GIO line, by the control operation of the main processor (641 in FIG. 31 ). The first buffer 751 may provide weight data to first to fourth MAC operators 731-734 and a vector engine 740, by the control operation from an internal instruction processor 720. The second buffer 752 may be coupled to a vector transmission line. The second buffer 752 may store vector data transmitted from the global buffer GB through the vector transmission line, by the control operation of the main processor (641 in FIG. 31 ). The second buffer 752 may provide vector data to the first to fourth MAC operators 731-734 and the vector engine 740, by the control operation from the internal instruction processor 720. The third buffer 753 may store arithmetic result data transmitted from the first to fourth MAC operators 731-734 and the vector engine 740, by the control operation of the internal processor 720. The third buffer 753 may output the operation result data to the GIO line.

In the first processing element PE0(2) according to the present example, the first to fourth MAC operators 731-734 may receive weight data and vector data from the first memory bank BK0 and the global buffer GB through the GIO line and the vector transmission line, respectively, to perform MAC arithmetic operations. In addition, the first to fourth MAC operators 731-734 may receive weight data and vector data from the first buffer 751 and the second buffer 752, respectively, to perform MAC arithmetic operations. The vector engine 740 may also receive the weight data and the vector data from the first memory bank BK0 and the global buffer GB through the GIO line and the vector transmission line, respectively, to perform a vector arithmetic operation. In addition, the vector engine 740 may receive the weight data and the vector data from the first buffer 751 and the second buffer 752, respectively, to perform a vector arithmetic operation.

When the first to “K−1”^(th) processing elements PE0-PE“K−1” of the PIM apparatus 600 described with reference to FIG. 31 is configured the same as the first processing element PE0(1) described with reference to FIG. 32 or the first processing element PE0(2) described with reference to FIG. 33 , the first to “K−1”^(th) processing elements PE0-PE“K−1” may perform different types of arithmetic operations according to the types of internal instructions stored in the internal instruction buffer.

FIG. 34 is a diagram illustrating a MAC arithmetic process in an accelerator mode of the PIM device 600 of FIG. 31 . Hereinafter, it is assumed that the PIM device 600 includes first to sixteenth processing elements PE0-PE15, that is, a case where “K” is “16”. In addition, as described with reference to FIGS. 32 and 33 , it is assumed that each of the first to sixteenth processing elements PE0-PE15 of the PIM device 600 includes first to fourth MAC operators and a vector engine.

Referring to FIG. 34 , the MAC arithmetic operation performed in the PIM device 600 may be performed as a matrix multiplication operation for a weight matrix 11 and a vector matrix 12. A result matrix 13 may be generated as a result of the MAC arithmetic operation in the PIM device 600. In an example, the weight matrix 11 may have the same number of rows as the number of processing elements PEs included in the PIM apparatus 600. In this example, because the PIM device 600 includes 16 processing elements PEs, the weight matrix 11 may have 16 rows. The weight matrix 11 may have the number of rows corresponding to a multiple of the number of processing elements PEs included in the PIM apparatus 600. For example, the weight matrix 11 may have the number of rows such as 32, 48, 64, 80, and the like. The weight matrix 11 may have the same number of columns as the number of rows of the vector matrix 12. In this example, a case in which the weight matrix 11 has 32 columns and the vector matrix 12 has 32 rows will be exemplified. The result matrix 13 in this case may have 32 rows and 1 column.

A first row of the weight matrix 11 may include 32 pieces of weight data W1.1-W1.32 (hereinafter, referred to as “first to 32^(nd) weight data of the first row”). Similarly, the sixteenth row of the weight matrix 11 may include 32 pieces of weight data W16.1-W16.32 (hereinafter, referred to as “first to 32^(nd) weight data of the sixteenth row”). In an example, the weight data W, which is an element of the weight matrix 11, may have a size of 16 bits. The first to 32^(nd) vector data V1-V32 may be arranged in the first to 32^(nd) rows of the vector matrix 12. The first to sixteenth result data RST1-RST16 may be arranged in the first to sixteenth rows of the result matrix 13.

Each column of the first to sixteenth rows of the weight matrix 11 may be divided into “L” groups. Here, “L” indicates the number of MAC operators included in the processing element PE. The data size of one group among the “L” groups may be the same as the size that can be processed in the process of performing one MAC arithmetic operation in one MAC operator. As described with reference to FIGS. 32 and 33 , as each of the first to sixteenth processing elements PE0-PE15 includes four MAC operators, that is, first to fourth MAC operators 731-734, each of the first to sixteenth rows of the weight matrix 11 may include four groups. As in this example, when each of the first to fourth MAC operators 731-734 can process eight pieces of weight data (i.e., 128-bit weight data) in the process of performing one MAC operation, each of the four groups included in each row of the weight matrix 11 may be composed of eight pieces of weight data (i.e., 128-bit weight data).

As illustrated in FIG. 34 , the first row of the weight matrix 11 may include first to fourth groups. That is, the weight data W1.1-W1.32 of the first row of the weight matrix 11 may be divided into units of eight pieces of weight data. Specifically, the weight data W1.1-W1.32 of the first row may be divided into a first group of weight data W1.1-W1.8, a second group of weight data W1.9-W1.16, a third group of weight data W1.17-W1.24, and a fourth group of weight data W1.25-W1.32. Similarly, the sixteenth row of the weight matrix 11 may also include first to fourth groups. That is, the weight data W16.1-W16.32 of the sixteenth row of the weight matrix 11 may be divided into a first group of weight data W16.1-W16.8, a second group of weight data W16.9-W16.16, a third group of weight data W16.17-16.24, and a fourth group of weight data W16.25-W16.32.

The columns of the vector matrix 12 may be divided into “L”, that is, four groups. As illustrated in FIG. 34 , the columns of the vector matrix 12 may include first to fourth groups. That is, the first to 32^(nd) vector data V1-V32 of the vector matrix 12 may be divided into units of eight pieces of vector data. Specifically, the first to 32^(nd) vector data V1-V32 of the vector matrix 12 may be divided into a first group of vector data V1-V8, a second group of vector data V9-V16, a third group of vector data V17-V24, and a fourth group of vector data V25-V32.

When the operation instruction set that controls the execution of the MAC operation (hereinafter, a MAC operation instruction set) is stored in an internal instruction buffer (710 in FIGS. 32 and 33 ) of each of the first to sixteenth processing elements PE0-PE15 of the PIM device 600, an internal processor (720 in FIGS. 32 and 33 ) of each of the first to sixteenth processing elements PE0-PE15 may transmit an internal control signal (hereinafter, an internal MAC control signal) corresponding to the MAC operation instruction set to the first to fourth MAC operators 731-734, in response to an accelerator mode start signal START. The weight data W1.1-W1.32 of the first row of the weight matrix 11 may be transmitted from the first memory bank BK0 to the first to fourth MAC operators 731-734 of the first processing element PE0. The weight data W2.1-W2.32 of the second row of the weight matrix 11 may be transmitted from the second memory bank BK1 to the first to fourth MAC operators of the second processing element PE1. Similarly, the weight data W16.1-W16.32 of the sixteenth row of the weight matrix 11 may be transmitted from the sixteenth memory bank BK15 to the first to fourth MAC operators of the sixteenth processing element PE15. The first to 32^(nd) vector data V1-V32 of the vector matrix 12 may be commonly transmitted to the first to sixteenth processing elements PE0-PE15.

The weight data W1.1-W1.32 of the first row of the weight matrix 11 transmitted to the first processing element PE0 may be input to the first to fourth MAC operators 731-734 of the first processing element PE0 in units of groups. That is, the first group W1.1-W1.8 of the weight data W1.1-W1.32 of the first row may be input to the first MAC operator 731 of the first processing element PE0. The second group W1.9-W1.16 of the weight data W1.1-W1.32 of the first row may be input to the second MAC operator 732 of the first processing element PE0. The third group W1.17-W1.24 of the weight data W1.1-W1.32 of the first row may be input to the third MAC operator 733 of the first processing element PE0. In addition, the fourth group W1.25-W1.32 of the weight data W1.1-W1.32 of the first row may be input to the fourth MAC operator 734 of the first processing element PE0.

The first to 32^(nd) vector data V1-V32 of the vector matrix 12 transmitted to the first processing element PE0 may also be input to the first to fourth MAC operators 731-734 of the first processing element PE0 in units of groups. That is, the first group V1-V8 of the first to 32^(nd) vector data V1-V32 may be input to the first MAC operator 731 of the first processing element PE0. The second group V9-V16 of the first to 32^(nd) vector data V1-V32 may be input to the second MAC operator 732 of the first processing element PE0. The third group V17-V24 of the first to 32^(nd) vector data V1-V32 may be input to the third MAC operator 733 of the first processing element PE0. In addition, the fourth group V25-V32 of the first to 32^(nd) vector data V1-V32 may be input to the fourth MAC operator 734 of the first processing element PE0.

The first MAC operator 731 of the first processing element PE0 may perform a matrix multiplication operation for the first group W1.1-W1.8 of the weight data W1.1-W1.32 of the first row and the first group V1-V8 of the first to 32^(nd) vector data V1-V32 to generate first sub-result data. The second MAC operator 732 of the first processing element PE0 may perform a matrix multiplication operation for the second group W1.9-W1.16 of the weight data W1.1-W1.32 of the first row and the second group V9-V16 of the first to 32^(nd) vector data V1-V32 to generate second sub-result data. The third MAC operator 733 of the first processing element PE0 may perform a matrix multiplication operation for the third group W1.17-W1.24 of the weight data W1.1-W1.32 of the first row and the third group V17-V24 of the first to 32^(nd) vector data V1-V32 to generate third sub-result data. In addition, the fourth MAC operator 734 of the first processing element PE0 may perform a matrix multiplication operation for the fourth group W1.25-W1.32 of the weight data W1.1-W1.32 of the first row and the fourth group V25-V32 of the first to 32^(nd) vector data V1-V32 to generate fourth sub-result data. When all the first to fourth sub-result data generated from the first to fourth MAC operators 731-734 of the first processing element PE0 are added up, the first result data RST1 of the result matrix 13 may be generated.

The second result data RST2 of the result matrix 13 may be generated by the second processing element PE1 that performs the same operation process as that of the first processing element PE0. The third result data RST3 of the result matrix 13 may be generated by the third processing element PE2 that performs the same operation process as that of the first processing element PE0. The fourth to sixteenth result data RST4-RST16 of the result matrix 13 may be generated by the fourth to sixteenth processing elements PE3-PE15 in the same manner.

FIG. 35 is a timing diagram illustrating a normal mode operation and an accelerator mode operation of the PIM device 600 of FIG. 31 .

Referring to FIG. 35 , the PIM device 600 may operate in a normal mode or may operate in an accelerator mode according to an operation mode of a host. As illustrated in FIG. 35 , during the time period from a first time point T1 to a third time point T3, the PIM device 600 may operate in the normal mode. During the time period from the third time point T3 to a fourth time point T4, the PIM device 600 may operate in the accelerator mode. During the time period from the fourth time point T4 to a sixth time point T6, the PIM device 600 may operate in the normal mode again. While the PIM device 600 operates in the normal mode before operating in the accelerator mode (i.e., during the time period from the first time point T1 to the third time point T3), the host may perform a preparation operation for the normal mode operation and a special mode. While the PIM device 600 operates in the normal mode after operating in the accelerator mode (i.e., during the time period from the fourth time point T4 to the sixth time point T6), the host may perform a post operation after the special mode and the normal mode operation. However, this is only an example, and the preparation operation for the special mode and the post operation after the special mode of the host may be included in the normal mode operation before and after the accelerator mode operation.

Specifically, during the time period from the first time point T1 to the second time point T2 when the host performs the normal mode operation, the host may sequentially transmit a first load command LD1, a first store command ST1, and a second load command LD2 to a controller. The controller may sequentially transmit a first read command RD1, a first write command WT1, and a second read command RD2 to the PIM device 600 in response to the first load command LD1, the first store command ST1, and the second load command LD2. The controller may transmit a refresh command REF to the PIM device 600 at an appropriate timing. In this example, the controller may transmit a first refresh command REF1 to the PIM device 600 after the first write command WT1 is transmitted to the PIM device 600 and before the second read command RD2 is transmitted to the PIM device 600. The PIM device 600 may perform a first read operation according to the first read command RD1, a first write operation according to the first write command WT1, a first refresh operation according to the first refresh command REF1, and a second read operation according to the second read command RD2.

During the time period from the second time point T2 to the third time point T3 when the host performs the preparation operation for the special mode, the host may transmit a second store command ST2 and a third store command ST3 to the controller. After transmitting the third store command ST3 to the controller, the host may transmit a high-level special mode signal S to the controller. The controller may transmit a second write command WT2 and a third write command WT3 to the PIM device 600 in response to the second store command ST2 and the third store command ST3. The controller may transmit a second refresh command REF2 to the PIM device 600 before transmitting the third write command WT3. The controller may transmit a high-level special mode signal S transmitted from the host to the PIM device 600. The PIM device 600 may perform a second write operation according to the second write command WT2, a second refresh operation according to the second refresh command REF2, and a third write operation according to the third write command WT3. The operation mode of the PIM device 600 may be switched from the normal mode to the accelerator mode by the high-level special mode signal S transmitted from the controller at the third time point T3.

During the time period from the third time point T3 to the fourth time point T4 when the host performs the accelerator mode operation, the host may transmit a high-level accelerator mode start signal S, a third load command LD3, a fourth load command LD4, a fifth load command LD5, and a sixth load command LD6 to the controller. The high-level accelerator mode start signal S in this example may be the same as the accelerator mode start signal START described with reference to FIGS. 31 to 33 . The controller may transmit a high-level accelerator mode start signal S transmitted from the host to the PIM device 600. The controller might not transmit the third load command LD3, the fourth load command LD4, the fifth load command LD5, and the sixth load command LD6 that are transmitted from the host to the PIM device 600 in response to the high-level accelerator mode start signal (S) transmitted from the host. The controller may transmit only a third refresh command REF3 and a fourth refresh command REF4 to the PIM device 600. The PIM device 600 may operate in the accelerator mode, in response to the high-level accelerator mode start signal S transmitted from the controller. As illustrated in FIG. 35 , the PIM device 600 may sequentially perform a first MAC arithmetic operation MAC1, a second MAC arithmetic operation MAC2, a first vector arithmetic operation VEC1, and a second vector arithmetic operation VEC2. After performing the second vector arithmetic operation VEC2, the PIM device 600 may perform a third refresh operation and a fourth refresh operation according to the third refresh command REF3 and the fourth refresh command REF4. The PIM device 600 may transmit an accelerator mode end signal D generated in the PIM device 600 to the controller, after performing all arithmetic operations in the accelerator mode. The accelerator mode end signal D in this example may be the same as the accelerator mode end signal DONE described with reference to FIG. 32 . The controller may transmit an accelerator mode completion signal E to the host in response to the accelerator mode end signal D. The host may change the logic level of the accelerator mode start signal S from a logic “high” level to a logic “low” level in response to the accelerator mode completion signal E.

During the time period from the fourth time point T4 to the fifth time point T5 when the host performs the post operation after the special mode, the host may transmit a fourth store command ST4 and a seventh load command LD7 to the controller. The PIM device 600 performs the accelerator mode operation, so that the controller may transmit commands for which transmission to the PIM device 600 has been suspended to the PIM device 600. That is, during the time period from the third time point T3 to the fourth time point T4, the controller may transmit a third read command RD3, a fourth read command RD4, and a fifth read command RD5 corresponding to the third load command LD3, the fourth load command LD4, and the fifth load command LD5 that are transmitted from the host to the PIM device 600. The controller may transmit a fifth refresh command REF5 to the PIM device 600 before transmitting the fifth read command RD5. The PIM device 600 may perform a third read operation according to the third read command RD3, a fourth read operation according to the fourth read command RD4, a fifth refresh operation according to the fifth refresh command REF5, and a fifth read operation according to the fifth read command RD5.

During the time period from the fifth time point T5 to the sixth time point T6 when the host performs the normal mode operation again, the host might not transmit the load commands and the store commands to the controller. As the PIM device 600 performs the accelerator mode operation, the controller may transmit commands that have not yet been transmitted to the PIM device 600 among the commands pending transmission to the PIM device 600. That is, during the time period from the third time point T3 to the fourth time point T4, the controller may transmit a sixth read command RD6 corresponding to the sixth load command LD6 that is received from the host to the PIM device 600. In addition, during the time period from the fourth time point T4 to the fifth time point T5, the controller may transmit a fourth write command WT4 and a seventh read command RD7 corresponding to a fourth store command ST4 and a seventh load command LD7 that are received from the host to the PIM device 600. The controller may transmit a sixth refresh command REF6 to the PIM device 600 before transmitting the seventh read command RD7. The PIM device 600 may perform a sixth read operation according to the sixth read command RD6, a fourth write operation according to the fourth write command WT4, a sixth refresh operation according to the sixth refresh command REF6, and a seventh read operation according to the seventh read command RD7.

FIG. 36 is a block diagram illustrating a PIM device 700 according to further another embodiment of the present disclosure. In FIG. 36 , the same reference numerals as those in FIG. 31 denote the same components. Accordingly, hereinafter, configurations different from those of the PIM device 600 of FIG. 31 will be mainly described. Referring to FIG. 36 , the PIM device 700 may be different from the PIM device 600 of FIG. 31 in that the PIM device 700 further includes an external vector engine EVE. Other components may be the same as those of the PIM device 600 of FIG. 31 . Each of first to “K”^(th) processing elements PE0-PE“K−1” may be configured the same as the first processing element PE0(1) of FIG. 32 or the first processing element PE0(2) of FIG. 33 . The external vector engine EVE may communicate bidirectionally with a GIO line and a vector engine line. The external vector engine EVE may perform a reprocessing operation for the vector data generated in the first to “K”^(th) processing elements PE0-PE“K−1”. In this case, the external vector engine EVE may receive the vector data from a global buffer GB, may reprocess the received vector data, and may transmit the vector data back to the global buffer GB. In some cases, the external vector engine EVE may transmit the reprocessed vector data to the vector engine in each of the first to “K”^(th) processing elements PE0-PE“K−1”.

FIG. 37 is a block diagram illustrating a PIM device 800 according to further another embodiment of the present disclosure. In addition, FIG. 38 is a block diagram illustrating an example of a configuration of a first processing element PE0 of FIG. 37 . In FIG. 37 , the same reference numerals as those in FIG. 36 denote the same components. Accordingly, hereinafter, configurations different from those of the PIM device 700 of FIG. 36 will be mainly described.

Referring first to FIG. 37 , the PIM device 800 may include a processor unit 840 including a main processor 841 and an instruction buffer 842. The main processor 841 may transmit a request signal REQ to the instruction buffer 842 in response to an accelerator mode start signal START that is transmitted from a command decoder 610. The main processor 841 may transmit an operation instruction set OP_INS that is transmitted from the instruction buffer 842 to first to “K”^(th) processing elements PE0-PE“K−1”. The operation instruction set OP_INS that is output from the main processor 841 may be divided into a first operation instruction set OP_INS1 and a second operation instruction set OP_INS2. In an example, the first operation instruction set OP_INS1 may include instructions that instruct MAC arithmetic operations. In addition, the second operation instruction set OP_INS2 may include instructions that instruct vector arithmetic. The instruction buffer 842 may store the operation instruction set OP_INS that is transmitted during the normal mode operation of the PIM device 600. The instruction buffer 842 may receive the operation instruction set OP_INS through the GIO line. The instruction buffer 842 may transmit the stored operation instruction set OP_INS to the main processor 841 in response to the request signal REQ from the main processor 841.

As illustrated in FIG. 38 , the first processing element PE0 among the first to “K”^(th) processing elements PE0-PE“K−1” may include first to fourth MAC operators 931-934 and a vector engine 940. That is, apart from the first processing element described with reference to FIGS. 32 and 33 , the first processing element PE0 according to the present example might not include an internal instruction buffer and an internal processor. The first to fourth MAC operators 931-934 and the vector engine 940 may have the same configuration as the first to fourth MAC operators 731-734 and the vector engine 740 described with reference to FIGS. 32 and 33 , respectively. However, the first to fourth MAC operators 931-934 may receive the first operation instruction set OP_INS1 that is transmitted from the main processor (841 of FIG. 37 ). In addition, the vector engine 940 may receive the second operation instruction set OP_INS2 that is transmitted from the main processor (841 of FIG. 37 ). The first to fourth MAC operators 931-934 may perform MAC arithmetic operations using weight data and vector data that are transmitted through the GIO line and a vector transmission line, respectively, in response to the first operation instruction set OP_INS1. The vector engine 940 may perform a vector arithmetic operation using vector data transmitted through the vector transmission line in response to the second operation instruction set OP_INS2. The vector engine 940 may receive additional data required for the vector arithmetic operation through the GIO line. The description of the first processing element PE0 so far may be equally applied to the second to “K−1”^(th) processing elements PE1-PE“K−1”.

FIG. 39 is a block diagram illustrating a PIM device 900 according to further another embodiment of the present disclosure. In FIG. 39 , the same reference numerals as those in FIG. 37 denote the same components. Accordingly, hereinafter, redundant descriptions will be omitted below.

Referring to FIG. 39 , the PIM device 900 may include first to sixteenth memory banks BO-BK15 and first to fourth processing elements PE90-PE93. On the premise that the number of memory banks is a multiple of the number of processing elements, the numbers of memory banks and processing elements may be variously set. The plurality of memory banks may share one processing element. In this example, four memory banks may share one processing element. That is, the first to fourth memory banks BK0-BK3 may share the first processing element PE90. The fifth to eighth memory banks BK4-BK7 may share the second processing element PE91. The ninth to twelfth memory banks BK8-BK11 may share the third processing element PE93. The thirteenth to sixteenth memory banks BK12-BK15 may share the fourth processing element PE94. Each of the first to fourth processing elements PE90-PE93 may have the same configuration as the processing elements described with reference to FIG. 32 or 33 .

The first to fourth memory banks BK0-BK3 and the first processing element PE90 may constitute a first processing unit PU90. The fifth to eighth banks BK4-BK7 and the second processing element PE91 may constitute a second processing unit PU91. The ninth to twelfth memory banks BK8-BK11 and the third processing element PE93 may constitute a third processing unit PU92. In addition, the thirteenth to sixteenth memory banks BK12-BK15 and the fourth processing element PE94 may constitute a fourth processing unit PU93. Accordingly, the first processing element PE90 may receive weight data from the first to fourth memory banks BK0-BK3. The second processing element PE91 may receive weight data from the fifth to eighth memory banks BK4-BK7. The third processing element PE92 may receive weight data from the ninth to twelfth memory banks BK8-BK11. The fourth processing element PE93 may receive weight data from the thirteenth to sixteenth memory banks BK12-BK15. The first to fourth processing elements PE90-PE93 may receive vector data from a global buffer GB or an external vector engine EVE.

The operation of the PIM device 900 according to the present embodiment may be different from the operation of the PIM device 600 described with reference to FIG. 31 in that the MAC arithmetic operation or the vector arithmetic operation is performed in units of memory banks (hereinafter, referred to as “bank groups”) sharing one processing element. Accordingly, when each of the first to fourth processing elements PE90-PE93 is configured the same as the processing element described with reference to FIG. 32 or 33 , the first to fourth processing units PU90-PU93 may perform different operations from each other.

A limited number of possible embodiments for the present teachings have been presented above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions, and substitutions are possible. While this patent document contains many specifics, these should not be construed as limitations on the scope of the present teachings or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination. 

What is claimed is:
 1. A processing-in-memory (PIM) device comprising: memory banks configured to perform a read operation and a write operation in a normal mode, and to perform a first data providing operation in an accelerator mode; a global buffer configured to perform a second data providing operation in the accelerator mode; processing elements configured to perform at least one of a first arithmetic operation and a second arithmetic operation using at least one of the first data and the second data in the accelerator mode; a command decoder configured to output a normal mode control signal or an accelerator mode start signal; and a processor unit configured to store an operation instruction set transmitted from an external device, to transmit the operation instruction set to the processing elements, and to transmit the accelerator mode control signal to the processing elements.
 2. The PIM device of claim 1, wherein the memory banks include first to “K”th memory banks, the processing elements include first to “K”th processing elements, and the first to “K”th processing elements receive first to “K”th groups of the first data from the first to “K”th memory banks, respectively, in the accelerator mode, and wherein the “J”th processing element among the first to “K”th processing elements is configured to receive a “J”th group of the first data from the “J”th memory bank among the first to “K”th memory banks, wherein “K” is a natural number, and wherein “3” is a natural number from 1 to “K”.
 3. The PIM device of claim 2, wherein the first data includes weight data of a weight matrix having at least “K” rows, and wherein the “J”th group of the first data is composed of elements of the “J”th row of the weight matrix.
 4. The PIM device of claim 3, wherein each of the first to “K”th processing elements includes first to “L”th MAC operators that perform the first arithmetic and at least one vector engine that performs the second arithmetic, and wherein “L” is a natural number.
 5. The PIM device of claim 4, wherein the “J”th group of the first data includes at least first to “L”th sets, and wherein the first to “L”th MAC operators included in the “J”th processing element among the first to “K”th processing elements are configured to receive the first to “L”th sets of the “J”th group of the first data, respectively, from the “J”th memory bank.
 6. The PIM device of claim 5, wherein the second data includes vector data of a vector matrix having at least the same number of rows as columns of the weight matrix and at least one column, and the rows of the second data are divided into first to “L” sets, and wherein the first to “L”th MAC operators of each of the first to “K”th processing elements are configured to receive the first to “L”th set of the second data, respectively, from the global buffer.
 7. The PIM device of claim 4, wherein each of the first to “K”th processing elements includes: an internal instruction buffer configured to store the operation instruction set transmitted from the processor unit; and an internal processor configured to transmit an internal control signal corresponding to the operation instruction set stored in the internal instruction buffer to the first to “L”th MAC operators and the vector engine, in response to the accelerator mode start signal transmitted from the processor unit.
 8. The PIM device of claim 7, further comprising: a global input/output (GIO) line configured to transmit a first data from the first to “K”th memory banks to the first to “K”th processing elements; and a vector transmission line configured to transmit a second data from the global buffer to the first to “K”th processing elements.
 9. The PIM device of claim 8, wherein data transmission capacity of the vector transmission line is at least “L” times greater than data transfer capacity of the GIO line.
 10. The PIM device of claim 8, wherein each of the first to “K”th processing elements further includes: a first buffer coupled to the GIO line; a second buffer coupled to the vector transmission line; and a third buffer coupled to the GIO line and configured to store arithmetic result data transmitted from the first to “L”th MAC operators and the vector engine.
 11. The PIM device of claim 1, wherein the command decoder is configured to output a read control signal or a write control signal as the normal mode control signal to the first to “K”th memory banks, and is configured to output the accelerator mode start signal to the processor unit.
 12. The PIM device of claim 11, wherein the command decoder is configured to output a refresh control signal, and wherein the command decoder is configured to transmit the refresh control signal to the first to “K”th memory banks in the normal mode, and is configured to transmit the refresh control signal to the processor unit in the accelerator mode.
 13. The PIM device of claim 11, wherein the processor unit includes: a main processor configured to output the operation instruction set and the accelerator mode start signal to the processing elements; and an instruction buffer configured to store the operation instruction set, and to transmit the operation instruction set to the main processor in response to a request signal from the main processor.
 14. The PIM device of claim 1, further comprising an external vector engine configured to perform a reprocessing operation for vector result data from the processing elements.
 15. The PIM device of claim 14, further comprising: a global input/output (GIO) line configured to transmit a first data from the memory banks to the processing elements; and a vector transmission line configured to transmit a second data from the global buffer to the processing elements, wherein the external vector engine is configured to communicate bidirectionally with the GIO line and the vector transmission line.
 16. The PIM device of claim 1, wherein each of the processing elements includes: MAC operators configured to perform MAC arithmetic operations corresponding to a first operation instruction set transmitted from the processor unit; and a vector engine configured to perform vector arithmetic operations corresponding to a second operation instruction set transmitted from the processor unit.
 17. The PIM device of claim 16, further comprising: a global input/output (GIO) line configured to transmit a first data from the memory banks to the processing elements; and a vector transmission line configured to transmit a second data from the global buffer to the processing elements.
 18. The PIM device of claim 17, wherein data transmission capacity of the vector transfer line is larger than data transmission capacity of the GIO line.
 19. The PIM device of claim 17, wherein each of the processing elements further includes: a first buffer coupled to the GIO line; a second buffer coupled to the vector transmission line; and a third buffer coupled to the GIO line and configured to store arithmetic result data transmitted from the MAC operators and the vector engine.
 20. The PIM device of claim 17, wherein the processor unit includes: a main processor configured to output the first operation instruction set or the second operation instruction set to the processing elements in response to the accelerator mode start signal; and an instruction buffer configured to store the first operation instruction set and the second operation instruction set, and to transmit the first operation instruction set and the second operation instruction set to the main processor in response to a request signal from the main processor.
 21. The PIM device of claim 17, further comprising an external vector engine configured to perform a reprocessing operation for vector result data from the processing elements.
 22. The PIM device of claim 21, wherein the external vector engine is configured to communicate bidirectionally with the GIO line and the vector transmission line.
 23. The PIM device of claim 1, wherein the memory banks share one processing element. 